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ST62T63CB6 bảng dữ liệu(PDF) 11 Page - STMicroelectronics |
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11 / 83 page 11/83 ST6253C ST6263C ST6263B ST6260C ST6260B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4. EEPROM locations are accessed di- rectly by addressing these paged sections of data space. The EEPROM does not require dedicated instruc- tions for read or write access. Once selected via the Data RAM Bank Register, the active EEPROM page is controlled by the EEPROM Control Regis- ter (EECTL), which is described below. Bit E20FF of the EECTL register must be reset prior to any write or read access to the EEPROM. If no bank has been selected, or if E2OFF is set, any ac- cess is meaningless. Programming must be enabled by setting the E2ENA bit of the EECTL register. The E2BUSY bit of the EECTL register is set when the EEPROM is performing a programming cycle. Any access to the EEPROM when E2BUSY is set is meaningless. Provided E2OFF and E2BUSY are reset, an EEP- ROM location is read just like any other data loca- tion, also in terms of access time. Writing to the EEPROM may be carried out in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). In BMODE, one byte is accessed at a time, while in PMODE up to 8 bytes in the same row are programmed simultaneously (with conse- quent speed and power consumption advantages, the latter being particularly important in battery powered circuits). General Notes: Data should be written directly to the intended ad- dress in EEPROM space. There is no buffer mem- ory between data RAM and the EEPROM space. When the EEPROM is busy (E2BUSY = “1”) EECTL cannot be accessed in write mode, it is only possible to read the status of E2BUSY. This implies that as long as the EEPROM is busy, it is not possible to change the status of the EEPROM Control Register. EECTL bits 4 and 5 are reserved and must never be set. Care is required when dealing with the EECTL reg- ister, as some bits are write only. For this reason, the EECTL contents must not be altered while ex- ecuting an interrupt service routine. If it is impossible to avoid writing to this register within an interrupt service routine, an image of the register must be saved in a RAM location, and each time the program writes to EECTL it must also write to the image register. The image register must be written to first so that, if an interrupt oc- curs between the two instructions, the EECTL will not be affected. Table 4. Row Arrangement for Parallel Writing of EEPROM Locations Note: The EEPROM is disabled as soon as STOP instruction is executed in order to achieve the lowest power-consumption. Dataspace addresses. Banks 0 and 1. Byte 0 1 2 3 4 5 6 7 ROW7 38h-3Fh ROW6 30h-37h ROW5 28h-2Fh ROW4 20h-27h ROW3 18h-1Fh ROW2 10h-17h ROW1 08h-0Fh ROW0 00h-07h Up to 8 bytes in each row may be programmed simultaneously in Parallel Write mode. The number of available 64-byte banks (1 or 2) is device dependent. |
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