832

Audio ICs

BU1923 / BU1923F

FOutput data timing

The clock (RCLK) frequency is 1187.5Hz. Depending on

the state of the internal PLL clock, the data (RDATA) is

replaced in synchronous with either the rising or falling

edge of the clock. To read the data, you may choose ei-

ther the rising or falling edge of the clock as the refer-

ence. The data is valid for 416.7

µs. after the reference

clock edge.

QUAL pin operation: Indicates the quality of the demodu-

lated data.

(1)

Good data: HI

(2)

Poor data: LO

FElectrical characteristic curve