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AD5433YCP-REEL bảng dữ liệu(PDF) 8 Page - Analog Devices

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AD5433YCP-REEL bảng dữ liệu(HTML) 8 Page - Analog Devices

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AD5424/AD5433/AD5445
Rev. B | Page 8 of 32
9
12
DB4
DB1
10
11
DB3
DB2
1
2
3
4
5
6
7
8
20
13
14
15
16
17
18
19
AD5433
(Not to Scale)
IOUT1
IOUT2
GND
DB9
DB8
DB7
DB6
DB5
RFB
VREF
VDD
R/W
CS
NC
NC
DB0 (LSB)
NC = NO CONNECT
Figure 5. AD5433 Pin Configuration (TSSOP)
R/W
CS
NC
NC
DB0
GND
DB9
DB8
DB7
DB6
15
14
13
12
11
1
2
3
4
5
20 19 18 17 16
678 9 10
AD5433
TOP VIEW
PIN 1
INDICATOR
NC = NO CONNECT
Figure 6 AD5433 Pin Configuration (LFCSP).
Table 5. AD5433 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
IOUT1
DAC Current Output.
2
20
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
Ground.
4–13
2–11
DB9–DB0
Parallel Data Bits 9 to 0.
14, 15
12, 13
NC
Not Internally Connected.
16
14
CS
Chip Select Input. Active low. Use in conjunction with R/
W to load parallel data to the input latch or to read data
from the DAC register. Rising edge of
CS loads data.
17
15
R/
W
Read/Write. When low, used in conjunction with
CS to load parallel data. When high, use with CS to read back
contents of DAC register.
18
16
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
VREF
DAC Reference Voltage Input Terminal.
20
18
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
9
12
DB6
DB3
10
11
DB5
DB4
1
2
3
4
5
6
7
8
20
13
14
15
16
17
18
19
AD5445
(Not to Scale)
IOUT1
IOUT2
GND
DB11
DB10
DB9
DB8
DB7
RFB
VREF
VDD
R/W
CS
DB0 (LSB)
DB1
DB2
Figure 7. AD5445 Pin Configuration (TSSOP)
R/W
CS
DB0
DB1
DB2
GND
DB11
DB10
DB9
DB8
15
14
13
12
11
1
2
3
4
5
20 19 18 17 16
67 89 10
AD5445
TOP VIEW
PIN 1
INDICATOR
Figure 8. AD5445 Pin Configuration (LFCSP)
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
IOUT1
DAC Current Output.
2
20
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
Ground Pin.
4–15
2–13
DB11–DB0
Parallel Data Bits 11 to 0.
16
14
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from
the DAC register. Rising edge of CS loads data.
17
15
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS to read back contents
of DAC register.
18
16
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19
17
VREF
DAC Reference Voltage Input Terminal.
20
18
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.


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