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TS2PCIE2212ZAHR bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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TS2PCIE2212ZAHR bảng dữ liệu(HTML) 6 Page - Texas Instruments |
6 / 12 page www.ti.com PARAMETER MEASUREMENT INFORMATION CL (see Note A) TEST CIRCUIT S1 2 × VDD Open GND RL RL tPZL VOH − 0.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. 50 Ω VG1 VDD DUT 50 Ω VIN 50 Ω VG2 VI TEST RL S1 V∆ CL VCC VI tPLZ/tPZL 1.8 V ± 0.1 V 2 × VDD 100 Ω GND No Load 0.3 V Input Generator Input Generator VDD/2 VDD/2 VO tPHZ/tPZH 1.8 V ± 0.1 V GND 100 Ω VDD No Load 0.3 V Output Control (VIN) VDD VOH VOL + 0.3 V VOH VOL 0 V tPZH tPLZ tPHZ Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 y VDD (see Note B) VOL SA CTRL VDD/2 VDD/2 TS2PCIE2212 PCI Express™ SIGNAL SWITCH SCDS209 – JUNE 2006 (Enable and Disable Times) Figure 6. Test Circuit and Voltage Waveforms 6 Submit Documentation Feedback |
Số phần tương tự - TS2PCIE2212ZAHR |
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Mô tả tương tự - TS2PCIE2212ZAHR |
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