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ADS4146 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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ADS4146 bảng dữ liệu(HTML) 11 Page - Texas Instruments |
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11 / 79 page  Dn_Dn+1_P Dn_Dn+1_M GND Logic0 V ODL Logic1 V ODH V OCM ADS4126, ADS4129 ADS4146, ADS4149 www.ti.com SBAS483D – NOVEMBER 2009 – REVISED APRIL 2010 TIMING CHARACTERISTICS (1) With external 100 Ω termination. Figure 3. LVDS Output Voltage Levels TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF (2), and R LOAD = 100Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V. PARAMETER CONDITIONS MIN TYP MAX UNIT tA Aperture delay 0.6 0.8 1.2 ns Variation of aperture Between two devices at the same temperature and ±100 ps delay DRVDD supply tJ Aperture jitter 100 fS rms Time to valid data after coming out of STANDBY 5 25 µs mode Wakeup time Time to valid data after coming out of PDN GLOBAL 100 500 µs mode Clock Low-latency mode (default after reset) 10 cycles Low-latency mode disabled (gain enabled, offset Clock ADC latency(4) 16 correction disabled) cycles Low-latency mode disabled (gain and offset Clock 17 correction enabled) cycles DDR LVDS MODE(5)(6) tSU Data setup time(3) Data valid(7) to zero-crossing of CLKOUTP 0.75 1.1 ns Zero-crossing of CLKOUTP to data becoming tH Data hold time(3) 0.35 0.60 ns invalid(7) Input clock rising edge cross-over to output clock Clock propagation tPDI rising edge cross-over 3 4.2 5.4 ns delay 1MSPS ≤ sampling frequency ≤ 250MSPS Between two devices at the same temperature and Variation of tPDI ±0.6 ns DRVDD supply (1) Timing parameters are ensured by design and characterization but are not production tested. (2) CLOAD is the effective external single-ended load capacitance between each output pin and ground. (3) RLOAD is the differential load resistance between the LVDS output pair. (4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1. (5) Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) The LVDS timings are unchanged for low latency disabled and enabled. (7) Data valid refers to a logic high of 1.26V and a logic low of 0.54V. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149 |
Số phần tương tự - ADS4146 |
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Mô tả tương tự - ADS4146 |
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