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LM3S9L97-EBZ80-C1 bảng dữ liệu(PDF) 4 Page - Texas Instruments

tên linh kiện LM3S9L97-EBZ80-C1
Giải thích chi tiết về linh kiện  Stellaris짰 LM3S9L97 Microcontroller
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LM3S9L97-EBZ80-C1 bảng dữ liệu(HTML) 4 Page - Texas Instruments

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5.5.1
Instruction Register (IR) ................................................................................................. 96
5.5.2
Data Registers .............................................................................................................. 98
6
System Control ..................................................................................................... 100
6.1
Signal Description ....................................................................................................... 100
6.2
Functional Description ................................................................................................. 100
6.2.1
Device Identification .................................................................................................... 101
6.2.2
Reset Control .............................................................................................................. 101
6.2.3
Non-Maskable Interrupt ............................................................................................... 105
6.2.4
Power Control ............................................................................................................. 106
6.2.5
Clock Control .............................................................................................................. 106
6.2.6
System Control ........................................................................................................... 113
6.3
Initialization and Configuration ..................................................................................... 115
6.4
Register Map .............................................................................................................. 115
6.5
Register Descriptions .................................................................................................. 116
7
Hibernation Module .............................................................................................. 206
7.1
Block Diagram ............................................................................................................ 207
7.2
Signal Description ....................................................................................................... 207
7.3
Functional Description ................................................................................................. 208
7.3.1
Register Access Timing ............................................................................................... 209
7.3.2
Hibernation Clock Source ............................................................................................ 209
7.3.3
Battery Management ................................................................................................... 211
7.3.4
Real-Time Clock .......................................................................................................... 211
7.3.5
Non-Volatile Memory ................................................................................................... 211
7.3.6
Power Control Using HIB ............................................................................................. 212
7.3.7
Power Control Using VDD3ON Mode ........................................................................... 212
7.3.8
Initiating Hibernate ...................................................................................................... 212
7.3.9
Interrupts and Status ................................................................................................... 212
7.4
Initialization and Configuration ..................................................................................... 213
7.4.1
Initialization ................................................................................................................. 213
7.4.2
RTC Match Functionality (No Hibernation) .................................................................... 214
7.4.3
RTC Match/Wake-Up from Hibernation ......................................................................... 214
7.4.4
External Wake-Up from Hibernation .............................................................................. 214
7.4.5
RTC or External Wake-Up from Hibernation .................................................................. 215
7.4.6
Register Reset ............................................................................................................ 215
7.5
Register Map .............................................................................................................. 215
7.6
Register Descriptions .................................................................................................. 216
8
Internal Memory ................................................................................................... 233
8.1
Block Diagram ............................................................................................................ 233
8.2
Functional Description ................................................................................................. 233
8.2.1
SRAM ........................................................................................................................ 234
8.2.2
ROM .......................................................................................................................... 234
8.2.3
Flash Memory ............................................................................................................. 236
8.3
Flash Memory Initialization and Configuration ............................................................... 237
8.3.1
Flash Memory Programming ........................................................................................ 237
8.3.2
32-Word Flash Memory Write Buffer ............................................................................. 239
8.3.3
Nonvolatile Register Programming ............................................................................... 239
8.4
Register Map .............................................................................................................. 240
8.5
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 241
June 15, 2010
4
Texas Instruments-Advance Information
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