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LM3S9B95-EQC25-C1 bảng dữ liệu(PDF) 6 Page - Texas Instruments

tên linh kiện LM3S9B95-EQC25-C1
Giải thích chi tiết về linh kiện  Stellaris짰 LM3S9B95 Microcontroller
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LM3S9B95-EQC25-C1 bảng dữ liệu(HTML) 6 Page - Texas Instruments

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12.3
Initialization and Configuration ..................................................................................... 483
12.4
Register Map .............................................................................................................. 483
12.5
Register Descriptions .................................................................................................. 484
13
Analog-to-Digital Converter (ADC) ..................................................................... 506
13.1
Block Diagram ............................................................................................................ 507
13.2
Signal Description ....................................................................................................... 508
13.3
Functional Description ................................................................................................. 509
13.3.1 Sample Sequencers .................................................................................................... 509
13.3.2 Module Control ............................................................................................................ 510
13.3.3 Hardware Sample Averaging Circuit ............................................................................. 513
13.3.4 Analog-to-Digital Converter .......................................................................................... 513
13.3.5 Differential Sampling ................................................................................................... 515
13.3.6 Internal Temperature Sensor ........................................................................................ 518
13.3.7 Digital Comparator Unit ............................................................................................... 518
13.4
Initialization and Configuration ..................................................................................... 523
13.4.1 Module Initialization ..................................................................................................... 523
13.4.2 Sample Sequencer Configuration ................................................................................. 524
13.5
Register Map .............................................................................................................. 524
13.6
Register Descriptions .................................................................................................. 526
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 584
14.1
Block Diagram ............................................................................................................ 585
14.2
Signal Description ....................................................................................................... 585
14.3
Functional Description ................................................................................................. 587
14.3.1 Transmit/Receive Logic ............................................................................................... 588
14.3.2 Baud-Rate Generation ................................................................................................. 588
14.3.3 Data Transmission ...................................................................................................... 589
14.3.4 Serial IR (SIR) ............................................................................................................. 589
14.3.5 ISO 7816 Support ....................................................................................................... 590
14.3.6 Modem Handshake Support ......................................................................................... 590
14.3.7 LIN Support ................................................................................................................ 592
14.3.8 FIFO Operation ........................................................................................................... 593
14.3.9 Interrupts .................................................................................................................... 593
14.3.10 Loopback Operation .................................................................................................... 594
14.3.11 DMA Operation ........................................................................................................... 594
14.4
Initialization and Configuration ..................................................................................... 595
14.5
Register Map .............................................................................................................. 596
14.6
Register Descriptions .................................................................................................. 597
15
Synchronous Serial Interface (SSI) .................................................................... 646
15.1
Block Diagram ............................................................................................................ 647
15.2
Signal Description ....................................................................................................... 647
15.3
Functional Description ................................................................................................. 648
15.3.1 Bit Rate Generation ..................................................................................................... 649
15.3.2 FIFO Operation ........................................................................................................... 649
15.3.3 Interrupts .................................................................................................................... 649
15.3.4 Frame Formats ........................................................................................................... 650
15.3.5 DMA Operation ........................................................................................................... 657
15.4
Initialization and Configuration ..................................................................................... 658
15.5
Register Map .............................................................................................................. 659
June 14, 2010
6
Texas Instruments-Advance Information
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