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LM3S9L97-IQR50-C1T bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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LM3S9L97-IQR50-C1T bảng dữ liệu(HTML) 7 Page - Texas Instruments |
7 / 1219 page 15.2 Signal Description ....................................................................................................... 598 15.3 Functional Description ................................................................................................. 599 15.3.1 Bit Rate Generation ..................................................................................................... 600 15.3.2 FIFO Operation ........................................................................................................... 600 15.3.3 Interrupts .................................................................................................................... 600 15.3.4 Frame Formats ........................................................................................................... 601 15.3.5 DMA Operation ........................................................................................................... 608 15.4 Initialization and Configuration ..................................................................................... 609 15.5 Register Map .............................................................................................................. 610 15.6 Register Descriptions .................................................................................................. 611 16 Inter-Integrated Circuit (I2C) Interface ................................................................ 639 16.1 Block Diagram ............................................................................................................ 640 16.2 Signal Description ....................................................................................................... 640 16.3 Functional Description ................................................................................................. 641 16.3.1 I2C Bus Functional Overview ........................................................................................ 641 16.3.2 Available Speed Modes ............................................................................................... 643 16.3.3 Interrupts .................................................................................................................... 644 16.3.4 Loopback Operation .................................................................................................... 645 16.3.5 Command Sequence Flow Charts ................................................................................ 645 16.4 Initialization and Configuration ..................................................................................... 652 16.5 Register Map .............................................................................................................. 653 16.6 Register Descriptions (I2C Master) ............................................................................... 654 16.7 Register Descriptions (I2C Slave) ................................................................................. 667 17 Inter-Integrated Circuit Sound (I2S) Interface .................................................... 676 17.1 Block Diagram ............................................................................................................ 677 17.2 Signal Description ....................................................................................................... 677 17.3 Functional Description ................................................................................................. 678 17.3.1 Transmit ..................................................................................................................... 680 17.3.2 Receive ...................................................................................................................... 684 17.4 Initialization and Configuration ..................................................................................... 686 17.5 Register Map .............................................................................................................. 687 17.6 Register Descriptions .................................................................................................. 688 18 Controller Area Network (CAN) Module ............................................................. 713 18.1 Block Diagram ............................................................................................................ 714 18.2 Signal Description ....................................................................................................... 714 18.3 Functional Description ................................................................................................. 715 18.3.1 Initialization ................................................................................................................. 716 18.3.2 Operation ................................................................................................................... 717 18.3.3 Transmitting Message Objects ..................................................................................... 718 18.3.4 Configuring a Transmit Message Object ........................................................................ 718 18.3.5 Updating a Transmit Message Object ........................................................................... 719 18.3.6 Accepting Received Message Objects .......................................................................... 720 18.3.7 Receiving a Data Frame .............................................................................................. 720 18.3.8 Receiving a Remote Frame .......................................................................................... 720 18.3.9 Receive/Transmit Priority ............................................................................................. 721 18.3.10 Configuring a Receive Message Object ........................................................................ 721 18.3.11 Handling of Received Message Objects ........................................................................ 722 7 June 15, 2010 Texas Instruments-Advance Information Stellaris® LM3S9L97 Microcontroller |
Số phần tương tự - LM3S9L97-IQR50-C1T |
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Mô tả tương tự - LM3S9L97-IQR50-C1T |
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