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SN74SSTUB32866ZKER bảng dữ liệu(PDF) 2 Page - Texas Instruments

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DESCRIPTION (CONTINUED)
SN74SSTUB32866
SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and
latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to
a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input
receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required
to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the
time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the
SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn
inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If
either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal
(LPS1) is high (one cycle after DCS and CSR go high), the device gates the QERR output from changing states.
If LPS1 is low, the QERR output functions normally. The RESET input has priority over the DCS and CSR control
and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control
functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement
for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input
should be pulled up to VCC through a pullup resistor.
The two VREF pins (A3 and T3) are connected together internally by approximately 150Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
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Copyright © 2006–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74SSTUB32866


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