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FEATURES

APPLICATIONS

DESCRIPTION/ORDERING INFORMATION

SN74SSQE32882

28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS PARITY TEST

ONE PAIR TO FOUR PAIR DIFFERENTIAL CLOCK PLL DRIVER

The SN74SSQE32882 has two basic modes of

operation associated with the Quad Chip Select

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• JEDEC SSTE32882 Compliant

Enable (QCSEN) input.

• 1-to-2 Register Outputs and 1-to-4 Clock Pair

First, when the QCSEN input pin is open or pulled

Outputs Support Stacked DDR3 DIMMs

high, the component has two chip select inputs,

• Chip Select Inputs Prevent Data Outputs from

DCS0 and DCS1, and two copies of each chip select

Changing State and Minimize System Power

output, QACS0, QACS1, QBCS0 and QBCS1. This

Consumption

mode is the QuadCS disabled mode. Alternatively,

when the QCSEN input pin is pulled low, the

• 1.5-V Phase Lock Loop Clock Driver Buffers

component has four chip select inputs DCS[3:0], and

One Differential Clock Pair (CK and CK) and

four chip select outputs, QCS[3:0]. This mode is the

Distributes to Four Differential Outputs

QuadCS enabled mode.

• 1.5-V CMOS Inputs

When QCSEN is high or floating, the device also

• Checks Parity on Command and Address

supports an operating mode that allows a single

(CS-gated) Data Inputs

device to be mounted on the back side of a DIMM

• Supports LVCMOS Switching Levels on

array. This device can then be configured to keep the

RESET Input

input bus termination (IBT) feature enabled for all

input

signals

independent

of

MIRROR.

The

• RESET Input:

SN74SSQE32882. operates from a differential clock

–

Disables Differential Input Receivers

(CK and CK). Data are registered at the crossing of

–

Resets All Registers

CK going high and CK going low. This data can either

be re-driven to the outputs or used to access internal

–

Forces All Outputs into Pre-defined States

control registers. Details are covered in the Function

• Optimal Pinout for DDR3 DIMM PCB Layout

Tables (each flip-flop) with QCSEN = low.

• Supports Four Chip Selects

Input bus data integrity is protected by a parity

• Single Register Backside Mount Support

function. All address and command input signals are

summed; the last bit of the sum is then compared to

the parity signal delivered by the system at the

• DDR3 Registered DIMMs up to DDR3-1333

PAR_IN input one clock cycle later. If these two

values do not match, the device pulls the open drain

• Single-, Dual- and Quad-Rank RDIMM

output ERROUT low. The control signals (DCKE0,

DCKE1, DODT0, DODT1, and DCS[n:0]) are not part

of this computation.

This JEDEC SSTE32882-compliant, 28-bit 1:2 or

The

SN74SSQE32882

implements

different

26-bit 1:2 and 4-bit 1:1 registering clock driver with

power-saving mechanisms to reduce thermal power

parity is designed for operation on DDR3 Registered

dissipation and to support system power-down states.

Power consumption is further reduced by disabling

All inputs are 1.5-V, CMOS-compatible. All outputs

unused outputs.

are 1.5-V CMOS drivers optimized to drive DRAM

The package design is optimal for high-density

signals on terminated traces in DDR3 RDIMM

DIMMs. By aligning input and output positions

applications. Clock outputs Yn and Yn and control net

towards DIMM finger-signal ordering and SDRAM

outputs DxCKEn, DxCSn, and DxODTn can each be

ballout, the device de-scrambles the DIMM traces

driven with a different strength and skew to optimize

and

allows

low

crosstalk

designs

with

low

signal integrity, compensate for different loading, and

interconnect latency. Edge-controlled outputs reduce

balance signal travel speed.

ringing and improve signal eye opening at the

SDRAM inputs.

1

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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.