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STM6502, STM6503, STM6504, STM6505
Description
Doc ID 16101 Rev 5
11/29
1.2.5
Edge-triggered Smart Reset input (SRE pin) – STM6504 only
The SRE pin is active-high, immediate and independent reset input that includes an edge
trigger with debounce delay tDEBOUNCE on the falling edge.
Note:
The triggering edge must be a high-to-low or low-to-high transition with a slew-rate faster
than 1 V/µs typ.
Figure 8.
STM6504 timing
1.2.6
Adjustable delay of Smart Reset input (SRC pin) – STM6502 and
STM6505 only
This pin controls the setup time before the push-button action is validated by the reset
output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the
desired value of the setup time (tSRC).
Calculated tSRC and CSRC examples are given in Table 3. Refer also to Table 6.
AM00328V2
tREC
SR0
t < tSRC
=> no output response
tSRC
t < tDEBOUNCE
=> tREC timer reset
Independent
RST
SRE
No debounce
tREC
tDEBOUNCE
(rising edges within
tDEBOUNCE are ignored)
tREC
Table 3.
tSRC programmed by an ideal external capacitor – STM6502 and STM6505
Calculated CSRC
value [µF]
Setup delay tSRC [s]
(1)(2)
1.
At 25 °C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external tSRC programming capacitor
(CSRC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
used and placed as close as possible to the SRC pin. Also an adequate low-leakage PCB environment
should be ensured to prevent tSRC accuracy from being affected. A recommended minimum value of CSRC
is 0.01 µF.
2.
In case of repeated activations of the tSRC timer, an interval of 10 ms min. is needed between the
activations to fully discharge CSRC, so that the next tSRC is as specified.
Closest common
CSRC value [µF]
Min.
Typ.
Max.
0.2
2
2.5
3.0
0.22
0.3
3
3.75
4.5
0.33
0.6
6
7.5
9
0.56
1
10
12.5
15
1


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