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STM6510VCACDG6F bảng dữ liệu(PDF) 10 Page - STMicroelectronics |
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10 / 26 page Description STM6510 10/26 Doc ID 16788 Rev 2 1.3.5 Reset output (RST) RST is active-low, open-drain. 1.3.6 Adjustable reset timeout (TRECADJ pin) The reset timeout (tREC) is adjustable by connecting an external capacitor CtREC to this pin. Calculated tREC and CtREC examples are given in Table 3. Refer also to Table 6. Table 3. tREC programmed by an ideal external capacitor Calculated CtREC value [µF] tREC [ms] (1)(2) 1. Example calculations based on an ideal capacitor. During application design and component selection it should be considered that the current flowing into the external tREC programming capacitor (CtREC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB environment should be used to prevent tREC accuracy from being affected. A recommended minimum value of CtREC is 0.001 µF. 2. In case of repeated activations of the tREC counter, an interval of 10 ms min. is needed between tREC intervals to fully discharge CtREC, so that the next tREC is as specified. Closest common CtREC value [µF] Min. Typ. Max. 0.001 10 15 20 0.001 0.002 20 30 40 0.0022 0.01 100 150 200 0.01 0.014 140 210 280 0.015 0.028 280 420 560 0.027 0.056 560 840 1120 0.056 0.112 1120 1680 2240 0.1 |
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