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STM6510LCACDG6F bảng dữ liệu(PDF) 6 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Dual push-button Smart ResetTM with capacitor-adjustable delays
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Description
STM6510
6/26
Doc ID 16788 Rev 2
Figure 1.
Logic diagram
Figure 2.
Pin connections
Table 1.
Signal names
Symbol
Input/output
Description
RST
Output
Reset output, active-low (open-drain).
SR0
Input
Primary push-button Smart Reset™ input. Active-low, internal 65 k
Ω
pull-up resistor to VCC.
SR1
Input
Secondary push-button Smart Reset™ input. Active-low, internal 65 k
Ω
pull-up resistor to VCC.
SRC
Input
Smart Reset™ input delay setup control. Connect an external capacitor
to this pin to adjust the delay setup time (tSRC).
TRECADJ
Input
Input pin for tREC reset pulse duration adjustment. Connect an external
capacitor (CtREC) to this pin to determine tREC.
VCC
Supply
Supply voltage input. Power supply for the device and an input for the
monitored supply voltage. A 0.1 µF decoupling ceramic capacitor is
recommended to be connected between VCC and VSS pins.
VSS
Supply
Ground
NC
No connect (not bonded); should be connected to VSS.
AM00389a
VCC
RST
TRECADJ
VSS
STM6510
SR1
SR0
SRC
AM00390
NC
TRECADJ
SRC
1
2
3
STM
6510
4
8
7
6
5
RST
VSS
VCC
SR1
SR0


Số phần tương tự - STM6510LCACDG6F

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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Mô tả tương tự - STM6510LCACDG6F

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