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MC14LC5004FU bảng dữ liệu(PDF) 5 Page - Motorola, Inc

tên linh kiện MC14LC5004FU
Giải thích chi tiết về linh kiện  72-Segment / 128-Segment LCD Drivers
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
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MC14LC5004FU bảng dữ liệu(HTML) 5 Page - Motorola, Inc

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3–7
MC14LC5002 • MC14LC5003 • MC14LC5004
MOTOROLA
ELECTRICAL CHARACTERISTICS (Continued)
NOTE: Timing for Figures 1, 2, and 3 are design estimates only.
* For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to
allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change.
Characteristic
Symbol
VDD
V
VLCD
V
Min
Typical
Max
Unit
Frequencies
OSC2 Frequency @ R1; R1 = 200 k
BP Frequency @ R1
OSC2 Frequency @ R2; R2 = 996 k
fOSC2
fBP
fOSC2
5
5
5
5
5
5
100
100
23
150
150
33
kHz
Hz
kHz
Average DC Offset Voltage (BP Relative to FP)
VOO
5
2.8
-50
+50
mV
Input Voltage
“0” Level
VIL
VIL
2.8
5.5
5
5
0.85
1.65
V
“1” Level
VIH
VIH
2.8
5.5
5
5
2
3.85
Output Drive Current — Backplanes VO = 2.65 V
IBH
*
IBL
5
5
2.8
2.8
-240
-240
µA
VO = 0.15 V
IBH
IBL
5
5
2.8
2.8
260
260
VO = 1.08V
IBH
IBL
5
5
2.8
2.8
40
2
VO = 1.72 V
IBH
IBL
5
5
2.8
2.8
-40
-1
VO = 5.35 V
IBH
IBL
5
5
5.5
5.5
-520
-520
VO = 0.15 V
IBH
IBL
5
5
5.5
5.5
600
600
VO = 1.98 V
IBH
IBL
5
5
5.5
5.5
55
1
VO = 3.52 V
IBH
IBL
5
5
5.5
5.5
-35
-1
Pulse Width, Data Clock
(Figure 1)
tw
5
3
100
100
ns
DCLK Rise/Fall Time
(Figure 1)
tr, tf
5
3
120
120
µs
Setup Time, Din to DCLK
(Figure 2)
tsu
5
3
20
20
ns
Hold Time, Din to DCLK
(Figure 2)
th
5
3
40
60
ns
Hold Time for START condition
(Figure 2)
tstart
5
3
100
100
ns
Hold Time for STOP condition
(Figure 2)
tstop
5
3
100
100
ns
DCLK Low to ENB High
(Figure 3)
th
5
3
20
20
ns
ENB High to DCLK High
(Figure 3)
trec
5
3
20
20
ns
ENB High Pulse Width
(Figure 3)
tw
5
3
100
100
ns
ENB Low to DCLK High
(Figure 3)
tsu
5
3
20
20
ns


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