công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADM1031ARQZ-REEL bảng dữ liệu(PDF) 4 Page - ON Semiconductor |
|
ADM1031ARQZ-REEL bảng dữ liệu(HTML) 4 Page - ON Semiconductor |
4 / 30 page ADM1031 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1) Parameter Unit Max Typ Min Test Conditions/Comments OPEN−DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL IOUT = –6.0 mA; VCC = 3.0 V 0.4 V High−Level Output Leakage Current, IOH VOUT = VCC 0.1 1.0 mA SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.1 V Input Low Voltage, VIL 0.8 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (Note 2) (ADD, THERM, TACH1/2) Input High Voltage, VIH 2.1 V Input Low Voltage, VIL 0.8 V DIGITAL INPUT LEAKAGE CURRENT Input High Current, IIH VIN = VCC –1.0 mA Input Low Current, IIL VIN = 0 1.0 mA Input Capacitance, CIN 5.0 pF FAN RPM−TO−DIGITAL CONVERTER Accuracy 60°C ≤ TA ≤ 100°C ±6.0 % Full−Scale Count 255 TACH Nominal Input RPM Divisor N = 1, Fan Count = 153 Divisor N = 2, Fan Count = 153 Divisor N = 4, Fan Count = 153 Divisor N = 8, Fan Count = 153 4400 2200 1100 550 RPM Conversion Cycle Time 637 ms SERIAL BUS TIMING (Note 3) Clock Frequency, fSCLK See Figure 2 10 100 kHz Glitch Immunity, tSW See Figure 2 50 ns Bus Free Time, tBUF See Figure 2 4.7 ms Start Setup Time, tSU;STA See Figure 2 4.7 ms Start Hold Time, tHD;STA See Figure 2 4.0 ms Stop Condition Setup Time, tSU;STO See Figure 2 4.0 ms SCL Low Time, tLOW See Figure 2 1.3 ms SCL High Time, tHIGH See Figure 2 4.0 50 ms SCL, SDA Rise Time, tR See Figure 2 1000 ns SCL, SDA Fall Time, tF See Figure 2 300 ns Data Setup Time, tSU;DAT See Figure 2 250 ns Data Hold Time, tHD;DAT See Figure 2 300 ns 1. Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V. 2. ADD is a three−state input that can be pulled high, low, or left open−circuit. 3. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge. Figure 2. Diagram for Serial Bus Timing P S tLOW tR tF tHD:STA tHD:DAT tSU:DAT tSU:STA tHD:STA tSU:STO tHIGH SCL PS SDA tBUF |
Số phần tương tự - ADM1031ARQZ-REEL |
|
Mô tả tương tự - ADM1031ARQZ-REEL |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |