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74HC138DR2G bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HC138/D
74HC138
1−of−8 Decoder/
Demultiplexer
High−Performance Silicon−Gate CMOS
The 74HC138 is identical in pinout to the LS138. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC138 decodes a three−bit Address to one−of−eight active−low
outputs. This device features three Chip Select inputs, two active−low
and one active−high to facilitate the demultiplexing, cascading, and
chip−selecting functions. The demultiplexing function is
accomplished by using the Address inputs to select the desired device
output; one of the Chip Selects is used as a data input while the other
Chip Selects are held in their active states.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 100 FETs or 29 Equivalent Gates
These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
1
16
1
16
1
16
HC138G
AWLYWW
HC
138
ALYW G
G
1
16
HC138
= Device Code
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or G
= Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)


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