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BU1571KN bảng dữ liệu(PDF) 5 Page - Rohm |
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BU1571KN bảng dữ liệu(HTML) 5 Page - Rohm |
5 / 9 page Technical Note BU1571KN 5/8 www.rohm.com 2010.06 - Rev.C © 2010 ROHM Co., Ltd. All rights reserved. ● Timing Chart 1. Two-line serial interface 1.1 Two-line serial interface timing Table 1 I 2C Interface timing Symbol Parameter MIN. TYP. MAX. Unit fSCL SDC Clock Frequency 0 - 400 kHz tHD;STA Hold-time(repetition)『START』conditions (The first clock pulse is generated after this period.) 0.6 - - µs fLOW The "L" period of SDC clock 1.3 - - µs tHIGH The "H" period of SDC clock 0.6 - - µs tSU;STA Setup time of repetitive 『START』conditions 0.6 - - µs tHD;DAT Hold time of SDA 0 - µs tSU;DAT Setup time of SDA 100 - - ns tSU;STO Setup time of the 『STOP』conditions 0.6 - - µs tBUF BUS free time between 『STOP』conditions and the 『START』conditions 1.3 - - µs 2. Camera module interface 2.1. Camera module interface timing The input timing of camera image signal on camera I/F is shown in Table 2. The input timing of camera image signal on camera I/F is shown in Table 2.1-2. Symbol Explanation MIN. TYP. MAX. UNIT tPCLK Clock Cycle 19.2 - - ns dPCLK Clock Duty 45 50 55 % tPDV Decision of CAMDO from CAMCKO - - 5 ns tPHL, tPHH Decision of CAMVSO or CAMHSO from CAMCKO - - 5 ns Symbol Explanation MIN. TYP. MAX. UNIT tCMS CAMCKI Rise / Fall Camera set-up Time 4 - - ns tCMH CAMCKI Rise / Fall Camera Hold Time 4 - - ns tLOW SDA SDC tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;ST tSU;STO tBUF Table 2. BU1571KN timing (Camera data input) Table 2. Camera data output timing CAMVSI CAMHSI CAMDI0 - CAMDI7 CAMCKI (CKPOL=“1”) CAMCKI (CKPOL=“0”) tCMS tCMH CAMVSO CAMDO[7:0] CAMHSO CAMCKO tPCLK tPHH tPHL tPDV |
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