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SM320C6713GHKS20EP bảng dữ liệu(PDF) 7 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
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SM320C6713-EP
SM320C6713B-EP
www.ti.com
SGUS049I – AUGUST 2003 – REVISED SEPTEMBER 2009
8-11
Oscillator Divider 1 (OSCDIV1) Register Description
....................................................................... 73
10-1
Characteristics of the Power-Down Modes
................................................................................... 83
10-2
C6713/13B Example Boards and Maximum EMIF Speed
.................................................................. 86
11-1
Board-Level Timings Example (see )
.......................................................................................... 92
11-2
Timing Requirements for CLKIN
............................................................................................... 93
11-3
Switching Characteristics for CLKOUT2
...................................................................................... 93
11-4
Switching Characteristics for CLKOUT3
...................................................................................... 94
11-5
Timing Requirements for ECLKIN
............................................................................................. 94
11-6
Switching Characteristics for ECLKOUT
..................................................................................... 95
11-7
Timing Requirements for Asynchronous Memory Cycles
.................................................................. 96
11-8
Switching Characteristics for Asynchronous Memory Cycles
............................................................. 96
11-9
Timing Requirements for Synchronous-Burst SRAM Cycles
.............................................................. 99
11-10
Switching Characteristics for Synchronous-Burst SRAM Cycles
.......................................................... 99
11-11
Timing Requirements for Synchronous DRAM Cycles
.................................................................... 100
11-12
Switching Characteristics for Synchronous DRAM Cycles
............................................................... 100
11-13
Timing Requirements for HOLD/HOLDA Cycles
........................................................................... 105
11-14
Switching Characteristics for HOLD/HOLDA Cycles
...................................................................... 105
11-15
Switching Characteristics for BUSREQ Cycles
............................................................................ 105
11-16
Timing Requirements for RESET
............................................................................................ 106
11-17
Switching Characteristics For RESET
....................................................................................... 106
11-18
Timing Requirements for External Interrupts
............................................................................... 108
11-19
Timing Requirements for McASP
............................................................................................ 109
11-20
Switching Characteristics for McASP
........................................................................................ 109
11-21
Timing Requirements for I
2C
................................................................................................. 112
11-22
Switching Characteristics for I
2C
............................................................................................. 113
11-23
Timing Requirements for Host-Port Interface Cycles
..................................................................... 114
11-24
Switching Characteristics for Host-Port Interface Cycles
................................................................. 115
11-25
Timing Requirements for McBSP
............................................................................................ 118
Copyright © 2003–2009, Texas Instruments Incorporated
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