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TS3L301DGG bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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TS3L301DGG bảng dữ liệu(HTML) 9 Page - Texas Instruments |
9 / 17 page www.ti.com PARAMETER MEASUREMENT INFORMATION CL (see Note A) TEST CIRCUIT S1 2 × VDD Open GND RL RL VOH VOL VOLTAGE WAVEFORMS OUTPUT SKEW [tsk(o)] Data Out at YB1 or YB2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. 50 Ω VG1 VDD DUT 50 Ω VIN 50 Ω VG2 50 Ω VI TEST RL S1 CL 3.3 V ± 0.3 V VDD VI tsk(p) tsk(o) 3.3 V ± 0.3 V Open Open 200 Ω 200 Ω VDD or GND VDD or GND 10 pF 10 pF Input Generator Input Generator VO (VOH + VOL)/2 VOH VOL Data Out at XB1 or XB2 (VOH + VOL)/2 3.5 V 1.5 V Data In at Ax or Ay 2.5 V tPLHx tPHLx tsk(o) tsk(o) tPLHy tPHLy tsk(o) = |tPLHy − tPLHx| or |tPHLy − tPHLx| VOH VOL VOLTAGE WAVEFORMS PULSE SKEW [tsk(p)] Output (VOH + VOL)/2 Input 2.5 V tPLH tPHL tsk(p) = |tPLH − tPLH| 3.5 V 1.5 V TS3L301 16-BIT TO 8-BIT SPDT GIGABIT LAN SWITCH WITH LOW AND FLAT ON-STATE RESISTANCE SCDS178C – NOVEMBER 2004 – REVISED APRIL 2006 (Skew) Figure 5. Test Circuit and Voltage Waveforms 9 Submit Documentation Feedback |
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