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1 / 170 page 1 SM320DM642-EP Video/Imaging Fixed-Point Digital Signal Processor 1.1 Features SM320DM642-EP Video/Imaging Fixed Point Digital Signal Processor www.ti.com SGUS058C – JUNE 2007 – REVISED JUNE 2009 – VelociTI.2™ Increased Orthogonality • Controlled Baseline • L1/L2 Memory Architecture – One Assembly/Test/Fabrication Site – 128K Bit (16K Byte) L1P Program Cache • Enhanced Diminishing Manufacturing Sources (Direct Mapped) (DMS) Support – 128K Bit (16K Byte) L1D Data Cache (2-Way • Enhanced Product-Change Notification Set-Associative) • Qualification Pedigree(1) – 2M Bit (256K Byte) L2 Unified Mapped • High-Performance Digital Media Processor RAM/Cache (Flexible RAM/Cache Allocation) – 2 ns, 1.67 ns, 1.39 ns Instruction Cycle Time • Endianess: Little Endian, Big Endian – 500 MHz, 600 MHz, 720 MHz Clock Rate – 64 Bit External Memory Interface (EMIF) (500/600 MHz devices are product preview – Glueless Interface to Asynchronous only) Memories (SRAM and EPROM) and – Eight 32-Bit Instructions/Cycle Synchronous Memories (SDRAM, SBSRAM, – 4000 MIPS, 4800 MIPS, 5760 MIPS ZBT SRAM, and FIFO) – Fully Software-Compatible With C64x™ • 1024M-Byte Total Addressable External • VelociTI.2™ Extensions to VelociTI™ Memory Space Advanced Very Long Instruction Word (VLIW) • Enhanced Direct-Memory-Access (EDMA) TMS320C64x™ DSP Core Controller (64 Independent Channels) – Eight Highly Independent Functional Units • 10/100 Mbps Ethernet MAC (EMAC) With VelociTI.2™ Extensions: – IEEE 802.3 Compliant • Six ALUs (32/40 Bit), Each Supports – Media Independent Interface (MII) Single 32 Bit, Dual 16 Bit, or Quad 8 Bit – Eight Independent Transmit (TX) Channels Arithmetic per Clock Cycle and One Receive (RX) Channel • Two Multipliers Support Four 16 × 16-Bit • Management Data Input/Output (MDIO) Multiplies (32 Bit Results) per Clock Cycle or Eight 8 × 8 Bit Multiplies (16 Bit • Three Configurable Video Ports Results) per Clock Cycle – Provide a Glueless I/F to Common Video – Load-Store Architecture With Non-Aligned Decoder and Encoder Devices Support – Supports Multiple Resolutions/Video Stds – 64 32-Bit General-Purpose Registers • VCXO Interpolated Control Port (VIC) – Instruction Packing Reduces Code Size – Supports Audio/Video Synchronization – All Instructions Conditional • Host Port Interface (HPI) [32/16 Bit] • Instruction Set Features • 32 Bit/66 MHz, 3.3-V Peripheral Component – Byte Addressable (8/16/32/64 Bit Data) Interconnect (PCI) Master/Slave Interface – 8-Bit Overflow Protection Conforms to PCI Specification 2.2 – Bit Field Extract, Set, Clear • Multichannel Audio Serial Port (McASP) – Normalization, Saturation, Bit-Counting – Eight Serial Data Pins (1) Component qualification in accordance with JEDEC and – Wide Variety of I2S and Similar Bit Stream industry standards to ensure reliable operation over an Format extended temperature range. This includes, but is not limited – Integrated Digital Audio I/F Transmitter to, Highly Accelerated Stress Test (HAST) or biased 85/85, Supports S/PDIF, IEC60958-1, AES-3, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound CP-430 Formats life. Such qualification testing should not be viewed as • Inter-Integrated Circuit (I2C Bus™) justifying use of this component beyond specified performance and environmental limits. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. C64x, VelociTI.2, VelociTI, TMS320C64x, C6000, TMS320C6000, DM64x, C62x, TMS320C62x, TMS320C67x, Code Composer Studio, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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