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MC68HC11EA9
8
MC68HC11EA9TS/D
3 Central Processing Unit
A full description of the CPU and instruction set of M68HC11 MCUs is beyond the scope of this sum-
mary. The programming model for the M68HC11 CPU and a brief description of the CPU registers is
provided here. For more detailed information refer to the
M68HC11 Reference Manual (M68HC11RM/
AD) or the programming reference guide or technical data book for the appropriate device.
3.1 Programming Model
Figure 4
shows a graphic representation of the internal registers of the M68HC11 CPU.
Figure 4 M68HC11 Programming Model
3.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory
locations. The seven registers, discussed briefly in the following paragraphs, are shown in Figure 4.
For a complete description of the CPU registers, addressing modes, and instruction set refer to the
M68HC11 Reference Manual (M68HC11RM/AD).
3.2.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic
calculations or data manipulations. For some instructions, these two accumulators are treated as a sin-
gle double-byte (16-bit) accumulator called accumulator D. Most instructions can use accumulators A
or B interchangeably, however some exceptions apply.
3.2.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an in-
struction to create an effective address. The IX register can also be used as a counter or as a temporary
storage register.
HC11 PROG MODEL
7
15
15
15
15
15
07
0
0
0
0
0
0
ACCUMULATOR A
ACCUMULATOR B
DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
CONDITION CODE REGISTER
SXH
I
N
Z
VC
CCR
A:B
D
IX
IY
SP
PC
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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