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ADRF6510ACPZ-R7 bảng dữ liệu(PDF) 4 Page - Analog Devices

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Giải thích chi tiết về linh kiện  30 MHz Dual Programmable Filters and Variable Gain Amplifiers
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ADRF6510ACPZ-R7 bảng dữ liệu(HTML) 4 Page - Analog Devices

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ADRF6510
Rev. 0 | Page 4 of 28
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
IMD3
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
61
dBc
Gain = 35 dB
57
dBc
IMD3 with Input CW Blocker
f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 5 MHz, 10 dBc
relative to two-tone composite output voltage
40
dBc
30 MHz Corner Frequency
Output Noise Density
Midband, gain = 0 dB
−130
dBV/√Hz
Midband, gain = 20 dB
−130
dBV/√Hz
Midband, gain = 40 dB
−123
dBV/√Hz
Second Harmonic, HD2
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
63
dBc
Gain = 40 dB
84
dBc
Third Harmonic, HD3
8 MHz fundamental, 1.5 V p-p output voltage
Gain = 0 dB
54
dBc
Gain = 40 dB
87
dBc
IMD3
f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite
output voltage
Gain = 5 dB
59
dBc
Gain = 35 dB
77.5
dBc
IMD3 with Input CW Blocker
f1 = 15 MHz, f2 = 16 MHz, 1.5 V p-p composite
output, gain = 5 dB; blocker at 150 MHz, 10 dBc
relative to two-tone composite output voltage
55
dBc
DIGITAL LOGIC
LE, CLK, DATA, SDO, OFDS, GNSW
Input High Voltage, VINH
>2
V
Input Low Voltage, VINL
<0.8
V
Input Current, IINH/IINL
<1
μA
Input Capacitance, CIN
2
pF
SPI TIMING
LE, CLK, DATA, SDO
fSCLK
1/tSCLK
20
MHz
tDH
DATA hold time
5
ns
tDS
DATA setup time
5
ns
tLH
LE hold time
5
ns
tLS
LE setup time
5
ns
tPW
CLK high pulse width
5
ns
tD
CLK to SDO delay
5
ns
POWER AND ENABLE
VPS, VPSD, COM, COMD, ENBL
Supply Voltage Range
4.75
5.0
5.25
V
Total Supply Current
ENBL = 5 V
Maximum bandwidth setting
258
mA
Minimum bandwidth setting
131
mA
Disable Current
ENBL = 0 V
2
mA
Disable Threshold
2.5
V
Enable Response Time
Delay following ENBL low-to-high transition
20
μs
Disable Response Time
Delay following ENBL high-to-low transition
300
ns


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