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MC9S08SH4CRTGR bảng dữ liệu(PDF) 11 Page - Freescale Semiconductor, Inc

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MC9S08SH4CRTGR bảng dữ liệu(HTML) 11 Page - Freescale Semiconductor, Inc

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MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
11
Section Number
Title
Page
6.3
Ganged Output ................................................................................................................................77
6.4
Pin Interrupts ...................................................................................................................................78
6.4.1
Edge Only Sensitivity .......................................................................................................78
6.4.2
Edge and Level Sensitivity ................................................................................................78
6.4.3
Pull-up/Pull-down Resistors .............................................................................................79
6.4.4
Pin Interrupt Initialization .................................................................................................79
6.5
Pin Behavior in Stop Modes ............................................................................................................79
6.6
Parallel I/O and Pin Control Registers ............................................................................................79
6.6.1
Port A Registers ................................................................................................................80
6.6.2
Port B Registers ................................................................................................................85
6.6.3
Port C Registers ................................................................................................................89
Chapter 7
Central Processor Unit (S08CPUV2)
7.1
Introduction .....................................................................................................................................93
7.1.1
Features .............................................................................................................................93
7.2
Programmer’s Model and CPU Registers .......................................................................................94
7.2.1
Accumulator (A) ...............................................................................................................94
7.2.2
Index Register (H:X) .........................................................................................................94
7.2.3
Stack Pointer (SP) .............................................................................................................95
7.2.4
Program Counter (PC) ......................................................................................................95
7.2.5
Condition Code Register (CCR) .......................................................................................95
7.3
Addressing Modes ...........................................................................................................................97
7.3.1
Inherent Addressing Mode (INH) .....................................................................................97
7.3.2
Relative Addressing Mode (REL) .....................................................................................97
7.3.3
Immediate Addressing Mode (IMM) ................................................................................97
7.3.4
Direct Addressing Mode (DIR) ........................................................................................97
7.3.5
Extended Addressing Mode (EXT) ..................................................................................98
7.3.6
Indexed Addressing Mode ................................................................................................98
7.4
Special Operations ...........................................................................................................................99
7.4.1
Reset Sequence .................................................................................................................99
7.4.2
Interrupt Sequence ............................................................................................................99
7.4.3
Wait Mode Operation ......................................................................................................100
7.4.4
Stop Mode Operation ......................................................................................................100
7.4.5
BGND Instruction ...........................................................................................................101
7.5
HCS08 Instruction Set Summary ..................................................................................................102
Chapter 8
Analog Comparator 5-V (S08ACMPV2)
8.1
Introduction ...................................................................................................................................113
8.1.1
ACMP Configuration Information ..................................................................................113
8.1.2
ACMP in Stop3 Mode .....................................................................................................113


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