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MC9S08SH8MFKRR bảng dữ liệu(PDF) 10 Page - Freescale Semiconductor, Inc

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MC9S08SH8MFKRR bảng dữ liệu(HTML) 10 Page - Freescale Semiconductor, Inc

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MC9S08SH8 MCU Series Data Sheet, Rev. 3
10
Freescale Semiconductor
Section Number
Title
Page
4.5.3
Program and Erase Command Execution .........................................................................48
4.5.4
Burst Program Execution ..................................................................................................49
4.5.5
Access Errors ....................................................................................................................51
4.5.6
FLASH Block Protection ..................................................................................................51
4.5.7
Vector Redirection ............................................................................................................52
4.6
Security ............................................................................................................................................52
4.7
FLASH Registers and Control Bits .................................................................................................53
4.7.1
FLASH Clock Divider Register (FCDIV) ........................................................................54
4.7.2
FLASH Options Register (FOPT and NVOPT) ................................................................55
4.7.3
FLASH Configuration Register (FCNFG) ........................................................................56
4.7.4
FLASH Protection Register (FPROT and NVPROT) .......................................................56
4.7.5
FLASH Status Register (FSTAT) ......................................................................................57
4.7.6
FLASH Command Register (FCMD) ...............................................................................58
Chapter 5
Resets, Interrupts, and General System Control
5.1
Introduction .....................................................................................................................................59
5.2
Features ...........................................................................................................................................59
5.3
MCU Reset ......................................................................................................................................59
5.4
Computer Operating Properly (COP) Watchdog .............................................................................60
5.5
Interrupts .........................................................................................................................................61
5.5.1
Interrupt Stack Frame .......................................................................................................62
5.5.2
External Interrupt Request Pin (IRQ) ...............................................................................63
5.5.3
Interrupt Vectors, Sources, and Local Masks ....................................................................63
5.6
Low-Voltage Detect (LVD) System ................................................................................................65
5.6.1
Power-On Reset Operation ...............................................................................................65
5.6.2
Low-Voltage Detection (LVD) Reset Operation ...............................................................65
5.6.3
Low-Voltage Warning (LVW) Interrupt Operation ...........................................................65
5.7
Reset, Interrupt, and System Control Registers and Control Bits ...................................................65
5.7.1
Interrupt Pin Request Status and Control Register (IRQSC) ............................................66
5.7.2
System Reset Status Register (SRS) .................................................................................67
5.7.3
System Background Debug Force Reset Register (SBDFR) ............................................68
5.7.4
System Options Register 1 (SOPT1) ................................................................................69
5.7.5
System Options Register 2 (SOPT2) ................................................................................70
5.7.6
System Device Identification Register (SDIDH, SDIDL) ................................................71
5.7.7
System Power Management Status and Control 1 Register (SPMSC1) ...........................72
5.7.8
System Power Management Status and Control 2 Register (SPMSC2) ...........................73
Chapter 6
Parallel Input/Output Control
6.1
Port Data and Data Direction ..........................................................................................................75
6.2
Pull-up, Slew Rate, and Drive Strength ...........................................................................................76


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