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MC9S08JS8L bảng dữ liệu(PDF) 7 Page - Freescale Semiconductor, Inc |
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MC9S08JS8L bảng dữ liệu(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 32 page  Electrical Characteristics MC9S08JS16 Series MCU Data Sheet, Rev. 4 Freescale Semiconductor 7 3.3 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. Table 4. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH -40 to 85 °C Thermal resistance 1,2,3,4 24-pin QFN 1s 2s2p 20-pin SOIC 1s 2s2p 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance 2 Junction to Ambient Natural Convection 3 1s — Single layer board, one signal layer 4 2s2p — Four layer board, 2 signal and 2 power layers θ JA 92 33 86 58 °C/W |
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