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MC9S08LH64 bảng dữ liệu(PDF) 1 Page - Freescale Semiconductor, Inc |
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MC9S08LH64 bảng dữ liệu(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 44 page  © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE 64-LQFP Case 840F 80-LQFP Case 917A • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range of –40 °C to 85 °C – Up to 20 MHz at 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources •On-Chip Memory – Dual array flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low-power stop modes – Reduced-power wait mode – Low-power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low-power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to time-of-day (TOD) module –6 μs typical wakeup time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 MHz to 20 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode detection with reset; illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes • Peripherals – LCD — Up to 8 ×36 or 4×40 LCD driver with internal charge pump and option to provide an internally-regulated LCD reference that can be trimmed for contrast control – ADC —16-bit resolution; with a dedicated differential ADC input, and 8 single-ended ADC inputs; up to 2.5 μs conversion time; hardware averaging; calibration registers, automatic compare function; temperature sensor; operation in stop3; fully functional from 3.6 V to 1.8 V – IIC — Inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcast mode; 10-bit addressing – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCIx — Two full-duplex non-return to zero (NRZ) modules (SCI1 and SCI2); LIN master extended break generation; LIN slave extended break detection; wakeup on active edge – SPI — Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting – TPMx — Two 2-channel (TPM1 and TPM2); selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel – TOD — (Time-of-day) 8-bit, quarter second counter with match register; external clock source for precise time base, time-of-day, calendar, or task scheduling functions – VREFx — Trimmable via an 8-bit register in 0.5 mV steps; automatically loaded with room temperature value upon reset; can be enabled to operate in stop3 mode; trim register is not available in stop modes • Input/Output – Dedicated accurate voltage reference output pin, 1.2 V output (VREFOx); trimmable with 0.5 mV resolution – Up to 39 GPIOs, two output-only pins – Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive strength on all output pins • Package Options – 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP Freescale Semiconductor Data Sheet: Advanced Information An Energy Efficient Solution by Freescale Document Number: MC9S08LH64 Rev. 4, 04/2010 MC9S08LH64 Series Covers: MC9S08LH64 and MC9S08LH36 |
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