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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SM320C6713BPYP300 bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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SM320C6713BPYP300 bảng dữ liệu(HTML) 2 Page - Texas Instruments |
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2 / 153 page  TMS320C6713B FLOATINGPOINT DIGITAL SIGNAL PROCESSOR SPRS294B − OCTOBER 2005 − REVISED JUNE 2006 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents EMIF device speed 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMIF big endian mode correctness 97 . . . . . . . . . . . . . . . . bootmode 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 99 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 99 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 100 parameter measurement information 101 . . . . . . . . . . . . . . signal transition levels 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . timing parameters and board routing analysis 103 . . . . . . input and output clocks 105 . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 108 . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing 111 . . . . . . . . . . . . . . . . . synchronous DRAM timing 113 . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 123 . . . . . . . . . . . . . . . . . . . . . . . . . multichannel audio serial port (McASP) timing 124 . . . . . . inter-integrated circuits (I2C) timing 127 . . . . . . . . . . . . . . . host-port interface timing 129 . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing 132 . . . . . . . . . . . . timer timing 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing 143 . . . . JTAG test-port timing 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GDP and ZDP 272-Ball BGA package (bottom view) 5 . . . . . PYP PowerPAD QFP package (top view) 10 . . . . . . . . . . . . description 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 13 . . . . . . . . . . CPU (DSP core) description 14 . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 18 . . . . . . . . . . . . . . . . . . . . . . . signal groups description 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . configuration examples 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device support 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU CSR register description 68 . . . . . . . . . . . . . . . . . . . . . . . . cache configuration (CCFG) register description 70 . . . . . . . . interrupts and interrupt selector 71 . . . . . . . . . . . . . . . . . . . . . . . external interrupt sources 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . EDMA module and EDMA selector 74 . . . . . . . . . . . . . . . . . . . . PLL and PLL controller 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multichannel audio serial port (McASP) peripherals 84 . . . . . I2C 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) 90 . . . . . . . . . . . . . . . . . . power-down mode logic 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 95 . . . . . . . . . . . . . power-supply decoupling 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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