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Giải thích chi tiết về linh kiện  PLL with band gap controlled VCO
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74HCT9046A_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 15 September 2009
10 of 43
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
When the frequencies of SIG_IN and COMP_IN are equal but the phase of SIG_IN leads
that of COMP_IN, the up output driver at PC2_OUT is held ‘ON’ for a time corresponding
to the phase difference (
Φ
PC_IN). When the phase of SIG_IN lags that of COMP_IN, the
down or sink driver is held ‘ON’.
a. At every
∆Φ, even at zero ∆Φ both switches are
closed simultaneously for a short period (typically
15 ns).
b. Comparable voltage-controlled switch
Fig 8.
The current switch charge pump output of PC2
mbd046
PC2_OUT
C2
V
CC
Icp
Icp
down
up
∆ Φ = Φ
PC_IN
pulse overlap of
approximately 15 ns
mbd099
R3'
Icp
up
down
C2
VCC
PC2_OUT
VC2_OUT
a. Current transfer
b. Voltage transfer. This transfer can be observed at
PC2_OUT by connecting a resistor (R = 10 k
Ω)
between PC2_OUT and 0.5VCC.
Fig 9.
Phase comparator 2 current and voltage transfer characteristics
001aak442
0
0
ΦPC_IN
+Icp
−Icp
−2π
+2π
001aak443
0
0.5VCC
0
VCC
VDEM_OUT(AV)
Icp × R
ΦPC_IN
−2π
+2π
pump current
I
cp
2
π
----------
Φ
PC _IN
V
DEM _OUT
V
=
PC 2_OUT
5
4
π
------
Φ
PC _IN
=
Φ
PC _IN
Φ
SIG_IN
Φ
COMP_IN
()
=


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