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74HC_HCT193_3
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 23 May 2007
7 of 29
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
(1) Clear overrides load, data and count inputs.
(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input
(CPU) must be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen, terminal count up, zero, one and two;
count down to one, zero, terminal count down, fifteen, fourteen and thirteen.
Fig 8.
Typical clear, load and count sequence
001aag411
COUNT UP
COUNT DOWN
013
CLEAR
PRESET
1
0
15
14
13
14
15
0
1
2
MR(1)
PL
D0
D1
D2
D3
CPU(2)
CPD(2)
Q0
Q1
Q2
Q3
TCU
TCD


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