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X1205S8 bảng dữ liệu(PDF) 11 Page - Xicor Inc. |
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X1205S8 bảng dữ liệu(HTML) 11 Page - Xicor Inc. |
11 / 22 page X1205 – Preliminary Information REV 1.0.9 8/29/02 Characteristics subject to change without notice. 11 of 22 www.xicor.com Random Read Random read operations allow the master to access any location in the X1205. Prior to issuing the Slave Address Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed by an acknowledge from the device and then by the eight bit data word. The master terminates the read operation by not responding with an acknowledge and then issu- ing a stop condition. Refer to Figure 10 for the address, acknowledge, and data transfer sequence. In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start shown in Figure 10. The X1205 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data. Sequential Read Sequential reads can be initiated as either a current address read or random address read. The first data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indi- cating it requires additional data. The device continues to output data for each acknowledge received. The mas- ter terminates the read operation by not responding with an acknowledge and then issuing a stop condition. The data output is sequential, with the data from address n followed by the data from address n + 1. Refer to Figure 11 for the acknowledge and data trans- fer sequence. Figure 10. Random Address Read Sequence 0 Slave Address Word Address 1 A C K A C K S t a r t S t o p Slave Address Data A C K 1 S t a r t SDA Bus Signals from the Slave Signals from the Master A C K Word Address 0 1 1 1 1 1 1 11 00 0 0 0 0 0 1 0 1 1 0 1 Figure 11. Sequential Read Sequence Data (2) S t o p Slave Address Data (n) A C K A C K SDA Bus Signals from the Slave Signals from the Master 1 Data (n-1) A C K A C K (n is any integer greater than 1) Data (1) |
Số phần tương tự - X1205S8 |
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Mô tả tương tự - X1205S8 |
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