BU2098F, BU2090F, BU2090FS

Technical Note

6/12

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2009.06 - Rev.A

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Function

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Start condition

The start condition is a “HIGH” to “LOW” transition of the SDA line while SCL is “HIGH”.

○

Stop condition

The stop condition is a “LOW” to “HIGH” transition of the SDA line while SCL is “HIGH”.

Fig.2 Start / Stop condition

○

Acknowledge

The master (μp) puts a resistive “HIGH” level on the SDA line during the acknowledge clock pulse. The peripheral (audio

processor) that acknowledge has to pull-down (“LOW”) the SDA line during the acknowledge clock pulse, so that the SDA

line is stable “LOW” during this clock pulse.

The slave which has been addressed has to generate an acknowledgement after the reception of each byte, otherwise the

SDA line remains at the “HIGH” level during the ninth clock pulse time. In this case the master transmitter can generate the

STOP information in order to abort the transfer.

Fig.3 Acknowledge

SDA

SCL

S

Start

condition

P

Stop

condition

9

8

1

SCL

(from master)

SDA

(from master)

SDA

(from slave)

S

not confirm

ACK signal

confirm

clock for acknowledge