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REV. C

○ Recommended operating conditions

Parameter

Symbol

Min

Typ

Max

Unit

Parameter

Symbol

Min

Typ

Max

Unit

Power supply voltage 1

(DAC)

DAVDD

3.00

3.30

3.60

V

Input voltage range

（ADC）

VIN1

-0.3

-

ADVDD

+0.3

V

Power supply voltage 2

(ADC)

ADVDD

3.00

3.30

3.60

V

Input voltage range

（I2C-1）

VIN2

-0.3

-

I1VDD

+0.3

V

Power supply voltage 3

(I2C-1)

I1VDD

2.40

3.30

3.60

V

Input voltage range

（I2C-2）

VIN3

-0.3

-

I2VDD

+0.3

V

Power supply voltage 4

(I2C-2)

I2VDD

2.40

3.30

3.60

V

Input voltage range

（SD-CARD）

VIN4

-0.3

-

SDI1

VDD+0.3

V

Power supply voltage 5

(SD-CARD)

SDVDD

2.70

3.30

3.60

V

Input voltage range

（CAMERA）

VIN5

-0.3

-

CAVDD

+0.3

V

Power supply voltage 6

(CAMERA)

CAVDD

2.30

2.85

3.30

V

Input voltage range

（Other IO）

VIN6

-0.3

-

IOVDD

+0.3

V

Power supply voltage 7

(Other IO)

IOVDD

1.70

3.30

3.60

V

Output "H" Current

*1

IOH

-13

-

-

mA

Power supply voltage 8

(Digital CORE)

DVDD

1.45

1.50

1.55

V

Output "L Current

*1

IOL

-

-

13

mA

Operating temperature

range

Topr

-40

-

85

ºC

*1 Sum of absolute current of IOs in IOVDD system must be less than 100mA, and every sum of absolute current of IOs in CAVDD,

SDVDD, I1VDD and I2VDD system must be less than 26mA.

* Please supply power source in order of CORE(DVDD) → IO（IOVDD,CAVDD,SDVDD,I1VDD,I2VDD,ADVDD,DAVDD）

* Please keep RESETB terminal is LOW, until power supply is stable.

○ Electric characteristics

(

DAVSS=ADVSS=DVSS=0.0V, Ta=25ºC, fXIN=13.5MHz, fAXIN=16.384MHz, fSYS=41.0MHz(Internal Clock with PLL)

IOPWR is a generic name of I1VDD,I2VDD,SDVDD,CAVDD,IOVDD.)

Parameter

Symbol

Specification

Unit

Conditions

Min

Max

Common

Input frequency 1

fXIN

5.0

30.0

MHz

XIN (Duty 50±10%), When PLL is ON.

Input frequency 2

fAXIN

8.284

32.768

MHz

AXIN(Duty 50±10%)

Internal clock frequency 1

fSYS

-

41.0

MHz

When PLL is ON, Except I2S Audio Block

Internal clock frequency 2

ｆAUD

-

32.768

MHz

I2S Audio Block

Static consumption current

IDDST

-

200

μA

When all clock stop

Logic Block

Input "H" Leakcurrent

IIHL

-10

10

μAVIH=IOPWR

Input "L" Leak current

IIHL

-10

10

μAVIL=０V

Input Pull down "H" current 1

IIHPD1

25

100

μA

Pull down pin, VIH=IOVDD

Input Pull down "H" current 2

IIHPD2

25

100

μA

Pull down pin, VIH=CAVDD

Input Pull down "L" current

IILPD

-10

10

μA

Pull down pin, VIL=０V

Input ”H” voltage 1

VIH1

IOPWR×0.8

IOPWR+0.3

V

Normal Input

Input ”L” voltage 1

VIL1

-0.3

IOPWR×0.2

V

Normal Input

Input ”H” voltage 2

VIH2

IOPWR×0.85

IOPWR+0.3

V

Hysteresis input pin

(TIM_TRIG,NTRST,RESETB,BIT_SEL,TCM_SEL,AUTO_READ)

Input ”L” voltage 12

VIL2

-0.3

IOPWR×0.15

V

Output ”H” voltage 1

VOH1

IOPWR-0.4

IOPWR

V

IOH=-2.0mA(DC), Output except SD_CLK, When CAVDD=3.3V

Output ”L” voltage 1

VOL1

0.0

0.4

V

IOL=2.0mA(DC), Output except SD_CLK, When CAVDD=3.3V.

Output ”H” voltage 2

VOH2

IOPWR-0.4

IOPWR

V

IOH=-4.0mA(DC)、SD_CLK

Output ”L” voltage 2

VOL2

0.0

0.4

V

IOL=4.0mA(DC)、SD_CLK

DACBlock

DAC Bit Width

RES_DA

-

10

bits

DAC Operating current

IDDDA

32

42

mA

DAC Static consumption current

IDDSTDA

-

5

uA

Integral Non-linearity

INL_DA

-8.0

+8.0

LSB

Differential Non-linearity

DNL_DA

-2.0

+2.0

LSB

Full scale voltage

VFS_DA

1.1

1.4

V

ADCBlock

ADC Bit Width

RES_AD

-

8

bits

Input voltage range(Upper Limit)

VIN_AD_T

ADVDD×0.85

ADVDD×0.95

V

Input voltage range(Lower Limit)

VIN_AD_B

ADVDD×0.05

ADVDD×0.15

V

Integral Non-linearity

INL_AD

-2.0

+2.0

LSB

Differential Non-linearity

DNL_AD

-2.0

+2.0

LSB

Change Standard clock cycle

ｆADC

4.0

16.0

MHz

Change cycle

fsps

30.8K

123K

sps

Sample per second

Need 130*ADC_CLK for conversion by sweeping