ADCLK944

Rev. 0 | Page 9 of 12

THEORY OF OPERATION

CLOCK INPUTS

The ADCLK944 accepts a differential clock input and distrib-

utes it to all four LVPECL outputs. The maximum specified

frequency is the point at which the output voltage swing is 50%

of the standard LVPECL swing (see Figure 4).

The device has a differential input equipped with center-tapped,

differential, 100 Ω on-chip termination resistors. The input can

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended,

3.3 V operation only), and ac-coupled 1.8 V CMOS, LVDS, and

inputs (see Figure 20 and Figure 21).

Maintain the differential input voltage swing from approxi-

mately 400 mV p-p to no more than 3.4 V p-p. See Figure 18

through Figure 21 for various clock input termination schemes.

Output jitter performance is significantly degraded by an input

slew rate below 1 V/ns, as shown in Figure 11. The ADCLK944

is specifically designed to minimize added random jitter over a

wide input slew rate range. Whenever possible, clamp excessively

large input signals with fast Schottky diodes because attenuators

reduce the slew rate. Input signal runs of more than a few centi-

meters should be over low loss dielectrics or cables with good

high frequency characteristics.

CLOCK OUTPUTS

The specified performance necessitates using proper transmis-

sion line terminations. The LVPECL outputs of the ADCLK944

are designed to directly drive 800 mV into a 50 Ω cable or into

microstrip/stripline transmission lines terminated with 50 Ω

output stage is shown in Figure 12. The outputs are designed

for best transmission line matching. If high speed signals must

be routed more than a centimeter, either the microstrip or the

stripline technique is required to ensure proper transition times

and to prevent excessive output ringing and pulse-width-dependent

propagation delay dispersion.

Q

Q

Figure 12. Simplified Schematic Diagram

of the LVPECL Output Stage

Figure 13 through Figure 16 depict various LVPECL output

buffer should match VS_DRV.

ADCLK944

VS_DRV

LVPECL

50

Ω

50

Ω

Figure 13. DC-Coupled, 3.3 V LVPECL

Thevenin-equivalent termination uses a resistor network to provide

driver. In this case, VS_DRV on the ADCLK944 should equal

shown in Figure 14 results in a dc bias point of VS_DRV − 2 V,

the actual common-mode voltage is VS_DRV − 1.3 V because

there is additional current flowing from the ADCLK944 LVPECL

driver through the pull-down resistor.

VS_DRV

50

Ω

50

Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

ADCLK944

LVPECL

127

Ω

127

Ω

83

Ω

83

Ω

Figure 14. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination

LVPECL Y-termination (see Figure 15) is an elegant termination

scheme that uses the fewest components and offers both odd-

and even-mode impedance matching. Even-mode impedance

matching is an important consideration for closely coupled trans-

mission lines at high frequencies. Its main drawback is that it offers

limited flexibility for varying the drive strength of the emitter-

follower LVPECL driver. This can be an important consideration

when driving long trace lengths but is usually not an issue.

ADCLK944

VS_DRV

LVPECL

50

Ω

50

Ω

50

Ω

Figure 15. DC-Coupled, 3.3 V LVPECL Y-Termination

A

VS_DRV

100

Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100

Ω

0.1nF

0.1nF

DCLK944

200

Ω

200

Ω

Figure 16. AC-Coupled LVPECL with Parallel Transmission Line