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ADCLK944BCPZ-R2 bảng dữ liệu(PDF) 1 Page - Analog Devices |
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1 / 12 page 2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK944 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. FEATURES FEATURES Operating frequency: 7.0 GHz Operating frequency: 7.0 GHz Broadband random jitter: 50 fs rms Broadband random jitter: 50 fs rms On-chip input terminations On-chip input terminations Power supply (VCC − VEE): 2.5 V to 3.3 V Power supply (VCC − VEE): 2.5 V to 3.3 V APPLICATIONS APPLICATIONS Low jitter clock distribution Low jitter clock distribution Clock and data signal restoration Clock and data signal restoration Level translation Level translation Wireless communications Wireless communications Wired communications Wired communications Medical and industrial imaging Medical and industrial imaging ATE and high performance instrumentation ATE and high performance instrumentation FUNCTIONAL BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM LVPECL ADCLK944 REFERENCE REF VT Q0 Q0 Q1 Q1 Q2 V CLK Q2 Q3 Q3 CLK Figure 1. GENERAL DESCRIPTION The ADCLK944 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs. The ADCLK944 features four full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differen- tial output swing of 1.6 V. The ADCLK944 is available in a 16-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C. |
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