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MCF53015CMJ240J bảng dữ liệu(PDF) 6 Page - Freescale Semiconductor, Inc

tên linh kiện MCF53015CMJ240J
Giải thích chi tiết về linh kiện  Version 3 ColdFire짰 core with EMAC
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MCF53015CMJ240J bảng dữ liệu(HTML) 6 Page - Freescale Semiconductor, Inc

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MCF5301x Data Sheet, Rev. 3
Preliminary—Subject to Change Without Notice
Hardware Design Considerations
Freescale Semiconductor
6
3.2
USB Power Filtering
To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 2 should be
connected between the board EVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the
dedicated USBVDD pin as possible.
Figure 2. USB VDD Power Filter
NOTE
In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel
with those shown.
3.3
Supply Voltage Sequencing
Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SDVDD), PLL VDD (PVDD), and internal logic /
core VDD (IVDD). The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences.
Both SDVDD (2.5V or 1.8V) and EVDD are specified relative to IVDD.
Figure 3. Supply Voltage Sequencing and Separation Cautions
Board EVDD
0
Ω
0.1 µF
USB VDD Pin
10 µF
GND
EVDD, USBVDD (3.3V)
IVDD, PVDD
Time
3.3V
1.2V
0
Notes:
1 IV
DD should not exceed EVDD, SDVDD or PVDD by more than 0.4V at any time, including power-up.
2 Recommended that IV
DD/PVDD should track EVDD/SDVDD up to 0.9V then separate for completion of ramps
3 Input voltage must not be greater than the supply voltage (EV
DD, SDVDD, IVDD, or PVDD) by more than 0.5V
at any time, including during power-up.
4 Use 1 microsecond or slower rise time for all supplies.
1
2
2.5V
Supplies Stable
SDVDD (2.5V - DDR)
1.8V
SDVDD (1.8V - DDR)


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