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ST8016 bảng dữ liệu(PDF) 4 Page - Sitronix Technology Co., Ltd. |
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ST8016 bảng dữ liệu(HTML) 4 Page - Sitronix Technology Co., Ltd. |
4 / 28 page ST8016 Ver 2.0 Page 4/28 2008/05/07 5 BLOCK DIAGRAM 6 FUNCTIONAL OPERATIONS OF EACH BLOCK BLOCK FUNCTION Active Control In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. SP Conversion & Data Control In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. Data Latch Control In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. Data Latch In case of segment mode, latches the data on the data bus. The latch state of each LCD drive output pin is controlled by the control logic and the data latch control; 160 bits of data are read in 20 sets of 8 bits. Line Latch/ Shift Register In case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched at the falling edge of the LP signal, and are output to the level shifter block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. Level Shifter The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. 4-Level Driver Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 levels (V0, V12, V43 or VSS) based on the S/C, FR and /DISPOFF signals. Control Logic Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 160 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift. 160-BIT 4-LEVEL DRIVER 160-BIT LEVEL SHIFTER 160-BIT LINE LATCH/SHIFT REGISTER DATA LATCH CONTROL SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8) CONTROL LOGIC ACTIVE CONTROL LEVEL SHIFTER 8 BIT DATA LATCH DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7VDD VSS V43L V12L V0L Y160 Y159 Y2 Y1 V43R V12R V0R FR DISPOFF EIO1 EIO2 LP XCK L/R MD S/C 8 16 16 16 160 160 |
Số phần tương tự - ST8016 |
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Mô tả tương tự - ST8016 |
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