ST7033

Ver 1.1

11/39

2009/07/17

Serial Interface

Serial Mode

PS1

PS0

/CSB

A0

4-line SPI interface

L

H

/CSB

Used

3-line SPI interface

L

L

/CSB

Not Used

Fix to “H”

Table 4. Microprocessor Selection for Serial Interface

PS1= “L”, PS0= “H”: 4-line SPI interface

When the ST7033 is active (/CSB=”L”), serial data (D1) and serial clock (D0) inputs are enabled. When /CSB is “High”, the

internal 8-bit shift register and the 3-bit counter are reset. The display data/command indication is controlled by the register

selection pin (A0). The signals transferred on data bus will be display data when A0 is high and will be instruction when A0

is low. The read feature is not supported in this mode. Serial data on SDA (D1) is latched at the rising edge of serial clock

on SCLK (D0). After the eighth serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column

address pointer will be increased by one automatically after each byte of DDRAM access.

3-line SPI interface

When ST7033 is active (/CSB=”L”), SDA-out, SDA-in and SCL inputs are enabled. When ST7033 is not active (/CSB=”H”),

the internal 8-bit shift register and the 3-bit counter are reset. The A0 pin is not available in this mode. Before issuing serial

data, an A0 bit is required to indicate the access is data or instruction. The read feature is not supported in this mode except

ID code read feature. Serial data on SDA (D1) is latched at the rising edge of serial clock on SCLK (D0). After the eighth

serial clock, the serial data will be processed as 8-bit parallel data. The DDRAM column address pointer will be increased

by one automatically after each byte of DDRAM access.

Figure 3. 3-Line SPI Timing

Figure 2. 4-Line SPI Timing