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ST2204 bảng dữ liệu(PDF) 7 Page - Sitronix Technology Co., Ltd.

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Giải thích chi tiết về linh kiện  8 BIT Integrated Microcontroller with 512K Bytes ROM
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ST2204 bảng dữ liệu(HTML) 7 Page - Sitronix Technology Co., Ltd.

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ST2204
Ver 0.6
7/24
2008/11/10
6
6.. IIN
NT
TE
ER
RR
RU
UP
PT
T C
CO
ON
NT
TR
RO
OL
LL
LE
ER
R
The ST2204 supports 11 hardware internal/external interrupts
as well as one software interrupt Brk. There are 12 exception
vectors for these interrupts and another one for reset. All
interrupts are controlled by interrupt disable flag “I” (bit2 of
status register P), and initiate if “I” equals “0”. Hardware
interrupts are further controlled by interrupt enable register
IENA
. Setting bits of IENA enables respective interrupts.
The interrupt controller owns one priority arbitrator. When more
than one interrupts happen at the same time, the one with
lower priority number will be executed first. Refer to TABLE 6-1
for priorities of interrupts.
Once an interrupt event was enabled and then happens, the
CPU wakes up (if in either wait mode), and associated bit of
interrupt request register (IREQ) will be set. If “I” flag is cleared,
the related vector will be fetched and then the interrupt service
routine (ISR) will be executed. Interrupt request flag can be
cleared by two methods. One is to write “0” to IREQ, the other
is to initiate related interrupt service routine. Hardware will
automatically clear the Interrupt request flag. All interrupt
vectors are listed in TABLE 6-1.
TABLE 6-1 Interrupt Vectors
Name
Signal Source
Vector Address
Priority
Description
BRK
Internal
$7FFF,$7FFE
1
Software BRK operation vector
RESET
External
$7FFD,$7FFC
0
Reset vector
-
-
$7FFB,$7FFA
-
Reserved
INTX
External
$7FF9,$7FF8
6
PC0 edge interrupt
DAC
Internal
$7FF7,$7FF6
7
Reload DAC data interrupt
T0
Internal/External
$7FF5,$7FF4
8
Timer0 interrupt
T1
Internal/External
$7FF3,$7FF2
9
Timer1 interrupt
PT
External
$7FF1,$7FF0
10
Port-A transition interrupt
BT
Internal
$7FEF,$7FEE
11
Base Timer interrupt
LCD
Internal
$7FED,$7FEC
12
LCD Frame interrupt
-
-
$7FEB,$7FEA
-
Reserved
STX
External
$7FE9,$7FE8
2
SPI transmit buffer empty interrupt
SRX
External
$7FE7,$7FE6
3
SPI receive buffer ready interrupt
UTX
External
$7FE5,$7FE4
4
UART receiver interrupt
URX
External
$7FE3,$7FE2
5
UART transmitter interrupt


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