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MCF5271CAB100 bảng dữ liệu(PDF) 8 Page - Freescale Semiconductor, Inc

tên linh kiện MCF5271CAB100
Giải thích chi tiết về linh kiện  Integrated Microprocessor Hardware Specification
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
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MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
Design Recommendations
Freescale Semiconductor
8
5
Design Recommendations
5.1
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5271.
See application note AN1259, System Design and Layout Techniques for Noise Reduction in
Processor-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and board
impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the
PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace
and separation. Clocks get extra separation and more precise balancing.
5.2
Power Supply
•33
μF, 0.1 μF, and 0.01 μF across each power supply
Test
TEST
I
19
F5
PLL_TEST
I
Power Supplies
VDDPLL
I
87
M13
VSSPLL
I
84
L14
OVDD
I
1, 18, 32, 41, 55,
69, 81, 94, 105,
114, 128, 138,
145
E5, E7, E10, F7,
F9, G6, G8, H7,
H8, H9, J6, J8,
J10, K5, K6, K8
VSS
I
17, 31, 40, 54,
67, 80, 88, 93,
104, 113, 127,
137, 144, 160
A1, A14, E6, E9,
F6, F8, F10, G7,
G9, H6, J5, J7,
J9, K7, P1, P14
VDD
I
16, 53, 103
D6, F11, G4, L4
1 Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled
in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.
2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module
is not responsible for assigning these pins.
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name
GPIO
Alternate 1 Alternate 2 Dir.1
MCF5270
MCF5271
160 QFP
MCF5270
MCF5271
196 MAPBGA


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