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MCF5270CAB100 bảng dữ liệu(PDF) 11 Page - Freescale Semiconductor, Inc |
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MCF5270CAB100 bảng dữ liệu(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 42 page  Design Recommendations MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4 Freescale Semiconductor 11 5.7.1.2 Address Multiplexing See the SDRAM controller module chapter in the MCF5271 Reference Manual for details on address multiplexing. 5.7.2 Ethernet PHY Transceiver Connection The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 4. Table 3. Synchronous DRAM Signal Connections Signal Description SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. SD_SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAMW DRAM read/write. Asserted for write operations and negated for read operations. SD_CS[1:0] Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals. SD_CKE Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. BS[3:0] Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. CLKOUT Bus clock output. Connects to the CLK input of SDRAMs. Table 4. MII Mode Signal Description MCF5271 Pin Transmit clock ETXCLK Transmit enable ETXEN Transmit data ETXD[3:0] Transmit error ETXER Collision ECOL Carrier sense ECRS Receive clock ERXCLK Receive enable ERXDV Receive data ERXD[3:0] |
Số phần tương tự - MCF5270CAB100 |
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