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AZV99NBG bảng dữ liệu(PDF) 2 Page - Arizona Microtek, Inc

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Giải thích chi tiết về linh kiện  PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
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nhà sản xuất  AZM [Arizona Microtek, Inc]
Trang chủ  http://azmicrotek.com
Logo AZM - Arizona Microtek, Inc

AZV99NBG bảng dữ liệu(HTML) 2 Page - Arizona Microtek, Inc

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AZV99
June 2009 * REV - 13
www.azmicrotek.com
2
MLP 8, 2x2 mm Package, NA, NB & ND Options
The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN
¯¯¯). When the
EN
¯¯¯ input is LOW, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When EN
¯¯¯ is HIGH, the Q
¯ output
continues to pass data while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D
¯ input is internally
bonded directly to the VBB pin bypassing the 470Ω bias resistor.
TSSOP 8 Package (T), MLP 8 Package, (N)
The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When
the EN input is HIGH, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When EN is LOW, the Q
¯ output
continues to pass data while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D
¯ input is internally
bonded directly to the VBB pin bypassing the 470Ω bias resistor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
Q
D
4mA EA.
470
VBB
EN/EN
VEE
EN-SEL
CMOS/TTL
THRESHOLD
CS-SEL
QHG
Q
D
QHG
EN-SEL
EN/EN
¯¯¯
Q/Q
¯
QHG
Q
¯ HG
NC
NC
PECL Low or NC
PECL High or VCC
Data
Data
Data
High
Data
Low
VEE
1
VEE
1
CMOS/TTL Low, VEE or NC
CMOS/TTL High or VCC
2
Data
Data
High
Data
Low
Data
1 EN-SEL connections must be less than 1Ω.
2 An external ≤20kΩ pull-up resistor between EN and VCC ensures a
High when the EN pin is not driven.
CURRENT SOURCE TRUTH TABLE
CS-SEL
Q
Q
¯
NC
VEE
1
VCC
1
4mA typ.
8mA typ.
0
4mA typ.
8mA typ.
4mA typ.
1 CS-SEL connections must be less than 1Ω.
PIN DESCRIPTION
PIN
FUNCTION
D/D
¯
Data Inputs
Q/Q
¯
PECL Data Outputs
QHG/Q
¯ HG
LVDS Data Outputs
VBB
Reference Voltage Output
EN-SEL
Selects Enable Logic
EN/EN
¯¯
Enable Input
CS-SEL
Selects Q and Q
¯ Current Source Magnitude
VEE
Negative Supply
VCC
Positive Supply


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