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6T39007ANLGI bảng dữ liệu(PDF) 6 Page - Integrated Device Technology |
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6T39007ANLGI bảng dữ liệu(HTML) 6 Page - Integrated Device Technology |
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6 / 15 page  IDT6T39007A CLOCK DISTRIBUTION CIRCUIT DISTRIBUTION CIRCUITS IDT™ CLOCK DISTRIBUTION CIRCUIT 6 IDT6T39007A REV G 111009 Byte 1: Control Register Byte 2: Control Register Bit Description Type Power Up Condition Output(s) Affected Notes 7 PWRCTRL_CLK1 Divider SEL bit 7 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 6 PWRCTRL_CLK1 Divider SEL bit 6 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 5 PWRCTRL_CLK1 Divider SEL bit 5 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 4 PWRCTRL_CLK1 Divider SEL bit 4 RW 0 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 3 PWRCTRL_CLK1 Divider SEL bit 3 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 2 PWRCTRL_CLK1 Divider SEL bit 2 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 1 PWRCTRL_CLK1 Divider SEL bit 1 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz 0 PWRCTRL_CLK1 Divider SEL bit 0 RW 1 PWRCTRL_CLK1 Default is /15 to get 866.666 kHz from 13 MHz Bit Description Type Power Up Condition Output(s) Affected Notes 7 PWRCTRL_CLK2 Divider SEL bit 7 RW 0 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 6 PWRCTRL_CLK2 Divider SEL bit 6 RW 0 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 5 PWRCTRL_CLK2 Divider SEL bit 5 RW 1 PWRCTRL_CLK2 Default is /46 to get 282.6kHz from 13 MHz 4 PWRCTRL_CLK2 Divider SEL bit 4 RW 0 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz 3 PWRCTRL_CLK2 Divider SEL bit 3 RW 1 PWRCTRL_CLK1 Default is /46 to get 282.6kHz from 13 MHz |
Số phần tương tự - 6T39007ANLGI |
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Mô tả tương tự - 6T39007ANLGI |
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