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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MC56F8365 bảng dữ liệu(PDF) 3 Page - Freescale Semiconductor, Inc |
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MC56F8365 bảng dữ liệu(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 180 page  56F8365 Technical Data, Rev. 8 Freescale Semiconductor 3 Preliminary Table of Contents Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 56F8365/56F8165 Features . . . . . . . . . . . .5 1.2 Device Description. . . . . . . . . . . . . . . . . . . .8 1.3 Award-Winning Development Environment10 1.4 Architecture Block Diagram . . . . . . . . . . . .10 1.5 Product Documentation . . . . . . . . . . . . . . .13 1.6 Data Sheet Conventions . . . . . . . . . . . . . .14 Part 2 Signal/Connection Descriptions . . . . 14 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .18 Part 3 On-Chip Clock Synthesis (OCCS) . . . 36 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .36 3.2 External Clock Operation. . . . . . . . . . . . . .36 3.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . .38 Part 4 Memory Map . . . . . . . . . . . . . . . . . . . . 38 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .38 4.2 Program Map . . . . . . . . . . . . . . . . . . . . . . .39 4.3 Interrupt Vector Table . . . . . . . . . . . . . . . .41 4.4 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .44 4.5 Flash Memory Map . . . . . . . . . . . . . . . . . .45 4.6 EOnCE Memory Map. . . . . . . . . . . . . . . . .46 4.7 Peripheral Memory Mapped Registers . . .47 4.8 Factory Programmed Memory . . . . . . . . . .79 Part 5 Interrupt Controller (ITCN) . . . . . . . . . 79 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . .79 5.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.3 Functional Description . . . . . . . . . . . . . . . .80 5.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . .81 5.5 Operating Modes . . . . . . . . . . . . . . . . . . . .81 5.6 Register Descriptions. . . . . . . . . . . . . . . . .82 5.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .109 Part 6 System Integration Module (SIM) . . 110 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . .110 6.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . .110 6.3 Operating Modes . . . . . . . . . . . . . . . . . . .111 6.4 Operating Mode Register. . . . . . . . . . . . .111 6.5 Register Descriptions. . . . . . . . . . . . . . . .112 6.6 Clock Generation Overview . . . . . . . . . . .127 6.7 Power-Down Modes Overview . . . . . . . .127 6.8 Stop and Wait Mode Disable Function . .128 6.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Part 7 Security Features . . . . . . . . . . . . . . . 129 7.1 Operation with Security Enabled . . . . . . .129 7.2 Flash Access Blocking Mechanisms . . . .129 Part 8 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 Memory Maps . . . . . . . . . . . . . . . . . . . . . 133 8.3 Configuration. . . . . . . . . . . . . . . . . . . . . . 133 Part 9 Joint Test Action Group (JTAG) . . 138 9.1 JTAG Information . . . . . . . . . . . . . . . . . . 138 Part 10 Specifications . . . . . . . . . . . . . . . . 138 10.1 General Characteristics. . . . . . . . . . . . . . 138 10.2 DC Electrical Characteristics. . . . . . . . . . 143 10.3 AC Electrical Characteristics. . . . . . . . . . 148 10.4 Flash Memory Characteristics. . . . . . . . . 148 10.5 External Clock Operation Timing . . . . . . 149 10.6 Phase Locked Loop Timing. . . . . . . . . . . 149 10.7 Crystal Oscillator Timing . . . . . . . . . . . . . 150 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . . 150 10.9 Serial Peripheral Interface (SPI) Timing . 153 10.10 Quad Timer Timing . . . . . . . . . . . . . . . . . 157 10.11 Quadrature Decoder Timing . . . . . . . . . . 157 10.12 Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . . . . . . . 158 10.13 Controller Area Network (CAN) Timing . . 159 10.14 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 159 10.15 Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . . . . 161 10.16 Equivalent Circuit for ADC Inputs . . . . . . 163 10.17 Power Consumption . . . . . . . . . . . . . . . . 164 Part 11 Packaging . . . . . . . . . . . . . . . . . . . 166 11.1 56F8365 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . . 166 11.2 56F8165 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . . 169 Part 12 Design Considerations . . . . . . . . . 174 12.1 Thermal Design Considerations . . . . . . . 174 12.2 Electrical Design Considerations . . . . . . 175 12.3 Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . . . 176 Part 13 Ordering Information . . . . . . . . . . 178 |
Số phần tương tự - MC56F8365 |
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Mô tả tương tự - MC56F8365 |
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