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ADG1414BRUZ bảng dữ liệu(PDF) 8 Page - Analog Devices

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ADG1414
Rev. 0 | Page 8 of 20
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted.1
Table 6.
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t12
20
ns min
SCLK cycle time
t2
9
ns min
SCLK high time
t3
9
ns min
SCLK low time
t4
5
ns min
SYNC to SCLK active edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
5
ns min
SCLK active edge to SYNC rising edge
t8
15
ns min
Minimum SYNC high time
t9
5
ns min
SYNC rising edge to next SCLK active edge ignored
t10
5
ns min
SCLK active edge to SYNC falling edge ignored
t113
40
ns max
SCLK rising edge to SDO valid
t12
15
ns min
Minimum RESET pulse width
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V.
3 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams
t4
t3
SCLK
DIN
t1
t2
t5
t6
t7
t8
DB7
t9
t10
SYNC
t12
RESET
DB0
Figure 2. Serial Write Operation


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