Electrical Characteristics

MC9S08MP16 Series Data Sheet, Rev. 1

Freescale Semiconductor

11

2.5

ESD Protection and Latch-Up Immunity

Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,

normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure

that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.

All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During

the device qualification, ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).

A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete

DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot

temperature, unless instructed otherwise in the device specification.

2.6

DC Characteristics

This section includes information about power supply requirements and I/O pin characteristics.

Table 5. ESD and Latch-up Test Conditions

Model

Description

Symbol

Value

Unit

Human

Body

Series resistance

R1

1500

Ω

Storage capacitance

C

100

pF

Number of pulses per pin

—

3

Latch-up

Minimum input voltage limit

– 2.5

V

Maximum input voltage limit

7.5

V

Table 6. ESD and Latch-Up Protection Characteristics

No.

under typical conditions unless otherwise noted.

Symbol

Min

Max

Unit

1

Human body model (HBM)

± 2000

—

V

2

Charge device model (CDM)

± 500

—

V

3

± 100

—

mA

Table 7. DC Characteristics

Num C

Characteristic

Symbol

Condition

Min

Max

Unit

1

— Operating Voltage

2.7

—

5.5

V

2

(2)

ΔV

DDA

—0

±100

mV

3

(2)

ΔV

SSA

—0

±100

mV