ADCLK948 datasheet(6/12 Pages) AD

tên linh kiện	ADCLK948

Giải thích chi tiết về linh kiện	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

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ADCLK948

Rev. 0 | Page 6 of

12

1. NC = NO CONNECT.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

2. EPAD MUST BE SOLDERED TO VEE POWER PLANE.

PIN 1

INDICATOR

1

CLK0

2

CLK0

3

VREF0

4

VT0

5

CLK1

6

CLK1

7

VT1

8

VREF1

24 Q2

23 Q2

22 Q3

21 Q3

20 Q4

19 Q4

18 Q5

17 Q5

TOP VIEW

(Not to Scale)

ADCLK948

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CLK0

Differential Input (Positive) 0.

2

CLK0

Differential Input (Negative) 0.

3

VREF0

Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.

4

VT0

Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.

5

CLK1

Differential Input (Positive) 1.

6

CLK1

Differential Input (Negative) 1.

7

VT1

Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.

8

VREF1

Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.

9

NC

No Connection.

10, 15, 16, 25, 26, 31

VCC

Positive Supply Pin.

11, 12

Q7, Q7

Differential LVPECL Outputs.

13, 14

Q6, Q6

Differential LVPECL Outputs.

17, 18

Q5, Q5

Differential LVPECL Outputs.

19, 20

Q4, Q4

Differential LVPECL Outputs.

21, 22

Q3, Q3

Differential LVPECL Outputs.

23, 24

Q2, Q2

Differential LVPECL Outputs.

27, 28

Q1, Q1

Differential LVPECL Outputs.

29, 30

Q0, Q0

Differential LVPECL Outputs.

32

IN_SEL

Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.

(33)

EPAD

EPAD must be connected to VEE.

Số phần tương tự - ADCLK948

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