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ADCLK946BCPZ bảng dữ liệu(PDF) 6 Page - Analog Devices

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Giải thích chi tiết về linh kiện  Six LVPECL Outputs, SiGe Clock Fanout Buffer
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ADCLK946
Rev. 0 | Page 6 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
VEE
2
CLK
3
CLK
4
VREF
5
VT
6
VEE
15 Q3
16 Q2
17 Q2
18 VCC
14 Q3
13 VCC
ADCLK946
TOP VIEW
(Not to Scale)
NOTES:
1. EXPOSED PADDLE MUST BE CONNECTED TO VEE.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 6, 7, 12, 19
VEE
Negative Supply Pin.
2
CLK
Differential Input (Positive).
3
CLK
Differential Input (Negative).
4
VREF
Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs.
5
VT
Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs.
8, 9
Q5, Q5
Differential LVPECL Outputs.
10, 11
Q4, Q4
Differential LVPECL Outputs.
13, 18, 24
VCC
Positive Supply Pin.
14, 15
Q3, Q3
Differential LVPECL Outputs.
16, 17
Q2, Q2
Differential LVPECL Outputs.
20, 21
Q1, Q1
Differential LVPECL Outputs.
22, 23
Q0, Q0
Differential LVPECL Outputs.
EPAD
EPAD must be soldered to VEE.


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