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UC1825A bảng dữ liệu(PDF) 7 Page - Texas Instruments

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UC1825A bảng dữ liệu(HTML) 7 Page - Texas Instruments

  UC1825A Datasheet HTML 1Page - Texas Instruments UC1825A Datasheet HTML 2Page - Texas Instruments UC1825A Datasheet HTML 3Page - Texas Instruments UC1825A Datasheet HTML 4Page - Texas Instruments UC1825A Datasheet HTML 5Page - Texas Instruments UC1825A Datasheet HTML 6Page - Texas Instruments UC1825A Datasheet HTML 7Page - Texas Instruments UC1825A Datasheet HTML 8Page - Texas Instruments UC1825A Datasheet HTML 9Page - Texas Instruments  
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UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
General Oscillator Synchronization
Power MOSFET Drive Circuit
Two Units
Operational Waveforms
HIGH CURRENT OUTPUTS
Each
totem
pole
output
of
the
UC3823A,B
and
UC3825A,B can deliver a 2 amp peak current into a ca-
pacitive load. The output can slew a 1000pF capacitor 15
volts in approximately 20 nanoseconds. Separate collec-
tor supply (VC) and power ground (PGND) pins help de-
couple the IC's analog circuitry from the high power gate
drive noise. The use of 3 Amp Schottky diodes (1N5120,
USD245 or equivalent) as shown in the figure from each
output to both VC and PGND are recommended. The di-
odes clamp the output swing to the supply rails, neces-
sary with any type of inductive/capacitive load, typical of a
MOSFET gate. Schottky diodes must be used because a
low forward voltage drop is required. DO NOT USE stan-
dard silicon diodes.
Although a "single ended" device, two output drivers are
available on the UC3823A,B devices. These can be “par-
alleled” by the use of a one-half ohm (noninductive) resis-
tor connected in series with each output for a combined
peak current of 4 amps.
SYNCHRONIZATION
The oscillator can be synchronized by an external pulse
inserted in series with the timing capacitor. Program the
free running frequency of the oscillator to be 10 to 15%
slower than the desired synchronous frequency. The
pulse width should be greater than 10ns and less than
half the discharge time of the oscillator. The rising edge of
the CLK/LEB pin can be used to generate a synchroniz-
ing pulse for other chips. Note that, the CLK/LEB pin will
no longer accept an incoming synchronizing signal.
APPLICATIONS INFORMATION (cont.)
UDG-95111
UDG-95112
UDG-95113
UDG-95114


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