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UC1823B bảng dữ liệu(PDF) 5 Page - Texas Instruments

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UC1823B bảng dữ liệu(HTML) 5 Page - Texas Instruments

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UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
OSCILLATOR (cont.)
APPLICATIONS INFORMATION (cont.)
Oscillator Frequency vs. RT and CT Curve
Maximum Duty Cycle vs RT Curve
UDG-95104
UDG-95103
LEADING EDGE BLANKING
The UC3823A,B/3825A,B performs fixed frequency
pulse width modulation control. The UC3823A,B out-
puts operate together at the switching frequency and
can vary from 0 to some value less than 100%. The
UC3825A,B outputs are alternately controlled. During
every other cycle, one output will be off. Each output
then, switches at one-half the oscillator frequency, vary-
ing in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse
blanks both outputs low during the discharge time of
the oscillator. On the falling edge of the clock, the ap-
propriate output(s) is driven high. The end of the pulse
is controlled by the PWM comparator, current limit com-
parator, or the overcurrent comparator.
Normally the PWM comparator will sense a ramp
crossing a control voltage (error amp output) and termi-
nate the pulse. Leading edge blanking (LEB) causes
the PWM comparator to be ignored for a fixed amount
of time after the start of the pulse. This allows noise in-
herent with switched mode power conversion to be re-
jected. The PWM ramp input may not require any
filtering as result of leading edge blanking.
To program a Leading Edge Blanking period, connect a
capacitor, C, to CLK/LEB. The discharge time set by C
and the internal 10k resistor will determine the blanked
interval. The 10k resistor has a 10% tolerance. For
more accuracy, an external 2k 1% resistor, R, can be
added, resulting in an equivalent resistance of 1.66k
with a tolerance of 2.4%. The design equation is:
tLEB = 0.5 • (R | | 10k) • C.
Values of R less than 2k should not be used
Leading edge blanking is also applied to the current
limit comparator. After LEB, if the ILIM pin exceeds the
one volt threshold, the pulse is terminated. The over
current comparator, however, is not blanked. It will
catch catastrophic over current faults without a blanking
delay. Any time the ILIM pin exceeds 1.2V, the fault
latch will be set and the outputs driven low. For this rea-
son, some noise filtering may be required on the ILIM
pin.
LEB Operational Waveforms
UDG-95105


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