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UCC3958 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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UCC3958 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 8 page 4 UCC3958 -1/-2/-3/-4 APPLICATION INFORMATION Battery Voltage Monitoring The battery cell voltage is sampled every 12ms by con- necting a resistor divider across it and comparing the re- sulting voltage to a precision internal reference voltage. Under normal conditions (cell voltage is below Over Volt- age threshold and above Under Voltage threshold), the UCC3958 consumes approximately 7 µA of current and the internal MOSFET is turned on with an RDSON of 50m Ω. The UCC3958 contains an on-chip Charge Pump to ensure that the internal MOSFET gate is driven high for complete turn-on, reducing power losses. The charge pump switches and capacitors are all internal. When the cell voltage falls below the Under Voltage threshold for two consecutive samples, the IC discon- nects the load from the battery pack and enters a super low power mode (nominally 1 µA). The pack will remain in this state until it detects the application of a charger, at which point controlled charging is enabled. The require- ment of two consecutive readings below the UV thresh- old filters out momentary drops in cell voltage due to load transients, preventing nuisance trips. If the cell voltage exceeds the Over Voltage threshold for two consecutive samples, charging is disabled, however discharge current is still allowed. This feature of the IC is explained further in the section on Controlled Charge/ Discharge Mode. PIN DESCRIPTIONS BNEG: Connect the negative terminal of the battery to these pins. CBPS: This power supply bypass pin is connected to PACK+ through an internal 10k resistor. An external capacitor must be connected between this pin and BNEG. This capacitor functions as temporary charge storage for high current conditions (short circuit). Minimum capacitor value is 0.15 µF. This value should be increased if the CDLY cap is used. CDLY: Delay control pin for the short circuit protection feature. A capacitor connected between this pin and the BNEG pin will increase the time delay for sensing an over current condition. This adjustment may be useful in those applications where high peak load currents may momentarily exceed the protection circuit’s threshold and interruption of the battery current would be undesirable. The nominal delay time is set internally at 350 µs CEB: Chip Enable Bar. This pin is pulled low (wrt BNEG) by a 100nA current source. In order to disable the IC, the user must pull this pin high to PACK+. LPWARN: Low Power Warning Indicator. This pin is forced high when the battery voltage drops below VTLO (nominally 2.65V). This pin will stay high until the detected battery voltage goes above VTLO,orUV condition is declared. OVUVB: This pin is an overvoltage/undervoltage condition indicator. Under normal operating conditions this pin is tristated. When an overvoltage (OV) state is detected, this pin is pulled high. When undervoltage (UV) condition is detected, this pin is pulled low. PACK+: Connect to the positive terminal of the battery. This pin is available to the user. PACK-: These pins should be connected to the negative terminal of the battery pack (negative terminal available to the user). The internal FET switch connects this terminal to the BNEG terminal to give the battery pack user appropriate access to the battery. In an overcharged state, only discharge current is permitted. In an overdischarged state, only charge current is permitted. SUB: Do not connect. These pins must be electrically isolated from all other pins. These pins may be soldered to isolated copper pads for heatsinking. This will improve heat transfer, which may be necessary at high load currents. 0.00 0.02 0.04 0.06 0.08 0.10 2.6 3.0 3.4 3.8 4.2 CELL VOLTAGE Figure 1. Typical Rdson vs Cell Voltage (DP Package Pin 7 to Pin 10, at 25°C, 1 Amp Load) |
Số phần tương tự - UCC3958 |
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Mô tả tương tự - UCC3958 |
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